1

Data sheet acquired from Harris Semiconductor

SCHS198C

Features

• Maximum Frequency, Typically 60MHz

• Positive-Edge Clocking

• Overriding Reset

• Buffered Inputs and Outputs

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

Description

The ’HC4015 consists of two identical, independent, 4-stage

serial-input/parallel-output

registers.

Each

register

has

independent Clock (CP) and Reset (MR) inputs as well as a

single serial Data input. “Q” outputs are available from each

of the four stages on both registers. All register stages are D-

type, master-slave flip-flops. The logic level present at the

Data input is transferred into the first register stage and

shifted over one stage at each positive- going clock

transition. Resetting of all stages is accomplished by a high

level on the reset line.

The device can drive up to 10 low power Schottky equivalent

loads. The ’HC4015 is an enhanced version of equivalent

CMOS types.

Pinout

CD54HC4015

(CERDIP)

CD74HC4015

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

PACKAGE

CD54HC4015F3A

-55 to 125

16 Ld CERDIP

CD74HC4015E

-55 to 125

16 Ld PDIP

CD74HC4015M

-55 to 125

16 Ld SOIC

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

2CP

1MR

GND

1D

2MR

1CP

2D

November 1997 - Revised May 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

CD54HC4015, CD74HC4015

High Speed CMOS Logic

Dual 4-Stage Static Shift Register

[ /Title

(CD74

HC401

5)

/Sub-

ject

(High

Speed

CMOS

Logic

Dual

4-