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CAT1027ZI-28-GT2 датащи(PDF) 5 Page - Catalyst Semiconductor |
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CAT1027ZI-28-GT2 датащи(HTML) 5 Page - Catalyst Semiconductor |
5 / 20 page CAT1026, CAT1027 © Catalyst Semiconductor, Inc. 5 Doc. No. MD-3010 Rev. M Characteristics subject to change without notice CAPACITANCE TA = 25ºC, f = 1.0MHz, VCC = 5V Symbol Test Test Conditions Max Units COUT (1) Output Capacitance VOUT = 0V 8 pF CIN (1) Input Capacitance VIN = 0V 6 pF AC CHARACTERISTICS VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle (2) Symbol Parameter Min Max Units fSCL Clock Frequency 400 kHz tSP Input Filter Spike Suppression (SDA, SCL) 100 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs tR (1) SDA and SCL Rise Time 300 ns tF (1) SDA and SCL Fall Time 300 ns tHD; STA Start Condition Hold Time 0.6 µs tSU; STA Start Condition Setup Time (for a Repeated Start) 0.6 µs tHD; DAT Data Input Hold Time 0 ns tSU; DAT Data Input Setup Time 100 ns tSU; STO Stop Condition Setup Time 0.6 µs tAA SCL Low to Data Out Valid 900 ns tDH Data Out Hold Time 50 ns tBUF (1) Time the Bus must be Free Before a New Transmission Can Start 1.3 µs tWC (3) Write Cycle Time (Byte or Page) 5 ms Notes: (1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (2) Test Conditions according to “AC Test Conditions” table. (3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. |
Аналогичный номер детали - CAT1027ZI-28-GT2 |
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Аналогичное описание - CAT1027ZI-28-GT2 |
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