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ST92163R4B1E датащи(PDF) 9 Page - STMicroelectronics |
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ST92163R4B1E датащи(HTML) 9 Page - STMicroelectronics |
9 / 224 page 9/224 ST92163 - GENERAL DESCRIPTION INTRODUCTION (Cont’d) 1.1.1 Core Architecture The nucleus of the ST92163 is the enhanced ST9 Core that includes the Central Processing Unit (CPU), the register file, the interrupt and DMA con- troller, and the Memory Management Unit (MMU). Three independent buses are controlled by the Core: a 22-bit memory bus, an 8-bit register ad- dressing bus and a 6-bit interrupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the core. This multiple bus architecture makes the ST9 fam- ily devices highly efficient for accessing on and off-chip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as ac- cumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. Many opcodes specify byte or word operations, the hardware automatically handles 16-bit opera- tions and accesses. For interrupts or subroutine calls, the CPU uses a system stack in conjunction with the stack pointer (SP). A separate user stack has its own SP. The separate stacks, without size limitations, can be in on-chip RAM (or in Register File) or off-chip mem- ory. 1.1.2 Instruction Set The ST9 instruction set consists of 94 instruction types, including instructions for bit handling, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats. Instructions have been added to facilitate large program and data handling through the MMU, as well as to improve the performance and code density of C Function calls. 14 address- ing modes are available, including powerful indi- rect addressing capabilities. The bit-manipulation instructions of the ST9 are set, clear, complement, test and set, load, and var- ious logic instructions (AND, OR, and XOR). Math functions include add, subtract, increment, decre- ment, decimal adjust, multiply and divide. 1.1.3 External MEMORY INTERFACE The ST92163 device has a 16-bit external address bus allowing it to address up to 64K bytes of exter- nal memory. 1.1.4 OPERATING MODES To optimize performance versus the power con- sumption of the device, ST9 devices now support a range of operating modes that can be dynami- cally selected depending on the performance and functionality requirements of the application at a given moment. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU). Slow Mode. Power consumption can be signifi- cantly reduced by running the CPU and the periph- erals at reduced clock speed using the CPU Pres- caler and CCU Clock Divider. Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution un- til an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the CCU. In this mode, the power consumption of the device can be reduced by more than 95% (LP WFI). Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt mode. Stop Mode. Under user program control, (see Wake-up and Interrupt Management Unit), the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped) until program execution is woken up by an event on an external Wake-up pin. |
Аналогичный номер детали - ST92163R4B1E |
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Аналогичное описание - ST92163R4B1E |
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