AD9388A

Rev. B | Page 7 of 28

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to

3.465 V, CVDD = 1.71 V to 1.89 V; operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 3.

Parameter1, 2

Symbol

Test Conditions

Min

Typ

Max

Unit

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency

28.6363

MHz

Crystal Frequency Stability

±50

ppm

Horizontal Sync Input Frequency

14.8

110

kHz

LLC Frequency Range

12.825

170

MHz

xCL Frequency4

400

kHz

xCL Minimum Pulse Width High4

0.6

μs

xCL Minimum Pulse Width Low4

1.3

μs

Hold Time (Start Condition)

0.6

μs

Setup Time (Start Condition)

0.6

μs

xDA Setup Time4

100

ns

xCL and xDA Rise Times4

300

ns

xCL and xDA Fall Times4

300

ns

Setup Time (Stop Condition)

0.6

μs

xCL Frequency

100

kHz

xCL Minimum Pulse Width High

4

μs

xCL Minimum Pulse Width Low

4.7

μs

Hold Time (Start Condition)

4

μs

Setup Time (Start Condition)

4.7

μs

xDA Setup Time

250

ns

xCL and xDA Rise Times

1000

ns

xCL and xDA Fall Times

300

ns

Setup Time (Stop Condition)

4

μs

RESET FEATURE

Reset Pulse Width

5

ms

CLOCK OUTPUTS

LLC Mark Space Ratio

45:55

55:45

% duty

cycle

DATA AND CONTROL OUTPUTS

Data Output Transition Time SDR (CP)5

End of valid data to negative clock edge

2

ns

Negative clock edge to start of valid data

0.5

ns

SCLK Mark Space Ratio

45:55

55:45

% duty

cycle

LRCLK Data Transition Time

End of valid data to negative SCLK edge

10

ns

LRCLK Data Transition Time

Negative SCLK edge to start of valid data

10

ns

I2Sx Data Transition Time6

End of valid data to negative SCLK edge

5

ns

I2Sx Data Transition Time6

Negative SCLK edge to start of valid data

5

ns

MCLKOUT Frequency

4.096

24.576

MHz