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AD7492ARU-5 датащи(PDF) 4 Page - Analog Devices

номер детали AD7492ARU-5
подробное описание детали  1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC
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домашняя страница  http://www.analog.com
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AD7492ARU-5 датащи(HTML) 4 Page - Analog Devices

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REV. 0
AD7492
–4–
TIMING SPECIFICATIONS
1
Limit at TMIN, TMAX
Parameter
AD7492
AD7492-5
2
Unit
Description
tCONVERT
880
680
ns max
tWAKEUP
20
3
20
3
µs max
Partial Sleep Wake-Up Time
500
500
µs max
Full Sleep Wake-Up Time
t1
10
10
ns min
CONVST Pulsewidth
t2
10
10
ns max
CONVST to BUSY Delay, V
DD = 5 V
40
N/A
ns max
CONVST to BUSY Delay, V
DD = 3 V
t3
0
0
ns max
BUSY to
CS Setup Time
t4
4
0
0
ns max
CS to RD Setup Time
t5
20
20
ns min
RD Pulsewidth
t6
4
15
15
ns min
Data Access Time after Falling Edge of
RD
t7
5
8
8
ns max
Bus Relinquish Time after Rising Edge of
RD
t8
0
0
ns max
CS to RD Hold Time
t9
120
120
ns min
Acquisition Time
t10
100
100
ns min
Quiet Time
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V. See
Figure 1.
2The AD7492-5 is specified with V
DD = 4.75 V to 5.25 V.
3This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20
µs, but we cannot guarantee that the part
will sample within 0.5 LSB of the true analog input value. Therefore we recommend that the user does not start conversion until after the specified time.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5t
7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number i s then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200 A
IOL
200 A
IOH
CL
50pF
TO OUTPUT
PIN
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
(VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)


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