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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TSC251G1DXXX-L12CED датащи(PDF) 9 Page - TEMIC Semiconductors |
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TSC251G1DXXX-L12CED датащи(HTML) 9 Page - TEMIC Semiconductors |
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9 / 52 page  TSC87251G1A 9 Rev. A – September 21, 1998 6.2. Data Memory The TSC87251G1A implements 1 Kbyte of on–chip data RAM. Figure 5 shows the split of the internal and external data memory spaces. This memory is mapped in the data space just over the 32 bytes of registers area (see TSC80251 Programmers’ Guide). Hence, the part of the on–chip RAM located from 20h to FFh is bit addressable. This on–chip RAM is not accessible through the program/code memory space. For faster computation with the on–chip EPROM code of the TSC87251G1A, its upper 8 Kbytes are also mapped in the upper part of the region 00: if the On–Chip Code Memory Map configuration bit is cleared (EMAP# bit in UCONFIG1 byte, see Figure 7). However, if EA# is tied to a low level, the TSC87251G1A derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory (i.e. the upper 8 Kbytes of the lower 16 Kbytes of the segment FF:). If EMAP# bit is set, the on–chip EPROM is not accessible through the region 00:. All the accesses to the portion of the data space with no on–chip memory mapped onto are redirected to the external memory. FF:3FFFh FF:0000h 01:0000h 00:FFFFh 00:E000h Data External Memory Space On–chip Memory EPROM/OTPROM Code FF:FFFFh FF:4000h 00:0420h FE:FFFFh 8 Kbytes 8 Kbytes 1 Kbyte 32 bytes reg. EMAP#= 1 Data Segments 48 Kbytes 16 Kbytes 8 Kbytes 56 Kbytes RAM Data FE:0000h 01:FFFFh 64 Kbytes 64 Kbytes EMAP#= 0 EA#= 1 00:DFFFh FD:FFFFh 02:0000h Reserved EA#= 0 Figure 5. Data Memory Mapping 6.3. Special Function Registers The Special Function Registers (SFRs) of the TSC87251G1A derivatives fall into the categories detailed in Table 3 to Table 11. SFRs are placed in a reserved on–chip memory region S: which is not represented in the data memory mapping (Figure 5). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12. They are upward compatible with the SFRs of the standard 80C51 and the Intel’s 80C251Sx family. In this table, the C251 core registers are in italics and are described in the TSC80251 Programmer’s Guide. The other SFRs are described in the TSC80251G1 Design Guide. All the SFRs are bit–addressable using the C251 instruction set. |
Аналогичный номер детали - TSC251G1DXXX-L12CED |
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Аналогичное описание - TSC251G1DXXX-L12CED |
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