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STM6823MAWY6F датащи(PDF) 11 Page - STMicroelectronics |
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STM6823MAWY6F датащи(HTML) 11 Page - STMicroelectronics |
11 / 28 page STM6321/6322STM6821/6822/6823/6824/6825 Operation 11/28 2.3 Push-button reset input (STM6322/6821/6822/6823/6825) A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 25 on page 19) after it returns high. The MR input has an internal 52 k Ω pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used. 2.4 Watchdog input (STM6321/6821/6822/6823/6824) The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD (1.6 sec), the reset is asserted. The internal watchdog timer is cleared by either: 1. a reset pulse, or 2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns. The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting. Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and the maximum allowable load capacitance is 200 pF. 2.5 Applications information 2.5.1 Watchdog input current The WDI input is internally driven through a buffer and series resistor from the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog time-out period. When high, WDI can draw as much as 160µA. Pulsing WDI high at a low duty cycle will reduce the effect of the large input current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog time-out period by a low-high-low pulse from the counter chain. 2.5.2 Ensuring a valid reset output down to VCC =0 V The STM6xxx supervisors are guaranteed to operate properly down to VCC = 1 V. In applications that require valid reset levels down to VCC = 0, a pull-down resistor to active- low outputs (push/pull only, see Figure 12 on page 12) and a pull-up resistor to active-high outputs (push/pull only, see Figure 13 on page 12) will ensure that the reset line is valid while the reset output can no longer sink or source current. This scheme does not work with the open drain outputs of the STM6321/6322/6822. The resistor value used is not critical, but it must be large enough not to load the reset output when VCC is above the reset threshold. For most applications, 100 kΩ is adequate. |
Аналогичный номер детали - STM6823MAWY6F |
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Аналогичное описание - STM6823MAWY6F |
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