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STPD0175BTC3 датащи(PDF) 2 Page - STMicroelectronics |
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STPD0175BTC3 датащи(HTML) 2 Page - STMicroelectronics |
2 / 48 page STPC CLIENT 2/48 Issue 1.7 - February 8, 2000 • X86 Processor core • Fully static 32-bit 5-stage pipeline, x86 proc- essor with DOS, Windows and UNIX compat- ibility. • Can access up to 4GB of external memory. • KBytes unified instruction and data cache with write back and write through capability. • Parallel processing integral floating point unit, with automatic power down. • Clock core speeds up to of 75 MHz. • Fully static design for dynamic clock control. • Low power and system management modes. • Optimized design for 3.3V operation. • DRAM Controller • Integrated system memory and graphic frame memory. • Supports up to 128 MBytes system memory in 4 banks and as little as MBytes. • Supports 4MBytes, 8MBites, 16MBites, 32MBites single-sided and double-sided DRAM SIMMs. • Four quad-word write buffers for CPU to DRAM and PCI to DRAM cycles. • Four 4-word read buffers for PCI masters. • Supports Fast Page Mode & EDO DRAMs. • Programmable timing for DRAM parameters including CAS pulse width, CAS pre-charge time, and RAS to CAS delay. • 60, 70, 80 & 100ns DRAM speeds. • Memory hole size of 1 MByte to 8 MBytes supported for PCI/ISA buses. • Hidden refresh. To check if your memory device is supported by the STPC, please refer to Table 7-69 in the Programming Manual. • Graphics Controller • 64-bit windows accelerator. • Backward compatibility to SVGA standards. • Hardware acceleration for text, bitblts, trans- parent blts and fills. • Up to 64 x 64 bit graphics hardware cursor. • Up to 4MB long linear frame buffer. • 8-, 16-, and 24-bit pixels. • CRT Controller • Integrated 135MHz triple RAMDAC allowing up to 1024 x 768 x 75Hz display. • 8-, 16-, 24-bit per pixels. • Interlaced or non-interlaced output. • Video Pipeline • Two-tap interpolative horizontal filter. • Two-tap interpolative vertical filter. • Colour space conversion (RGB to YUV and YUV to RGB). • Programmable window size. • Chroma and colour keying allowing video overlay. • Programmable two tap filter with gamma cor- rection or three tap flicker filter. • Progressive to interlaced scan converter. • Video Input port • Decodes video inputs in ITU-R 601/656 com- patible formats. • Optional 2:1 decimator • Stores captured video in off setting area of the onboard frame buffer. • Video pass through to the onboard PAL/ NTSC encoder for full screen video images. • HSYNC and B/T generation or lock onto external video timing source. • PCI Controller • Integrated PCI arbitration interface able to directly manage up to 3 PCI masters at a time. • Translation of PCI cycles to ISA bus. • Translation of ISA master initiated cycle to PCI. • Support for burst read/write from PCI master. • The PCI clock runs at a third or half CPU clock speed. |
Аналогичный номер детали - STPD0175BTC3 |
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Аналогичное описание - STPD0175BTC3 |
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