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MC13202FC датащи(PDF) 5 Page - Freescale Semiconductor, Inc |
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MC13202FC датащи(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 30 page MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 5 Figure 2 shows the basic system block diagram for the MC13202 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements. Figure 2. System Level Block Diagram 4 Data Transfer Modes The MC13202 has two data transfer modes: 1. Packet Mode — Data is buffered in on-chip RAM 2. Streaming Mode — Data is processed word-by-word The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary applications, packet mode can be used to conserve MCU resources. 4.1 Packet Structure Figure 3 shows the packet structure of the MC13202. Payloads of up to 125 bytes are supported. The MC13202 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of the data. Figure 3. MC13202 Packet Structure Analog Receiver MC13202 Frequency Generation Analog Transmitter Voltage Regulators Power Up Management Control Logic Buffer RAM SPI and GPIO Microcontroller SPI ROM (Flash) RAM CPU A/D Application Network MAC PHY Driver Preamble SFD FLI Payload Data FCS 4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes |
Аналогичный номер детали - MC13202FC |
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Аналогичное описание - MC13202FC |
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