HORIZONTAL SECTION (continued)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

1st PLL SECTION

HpolT

Polarity Integration Delay

0.75

ms

VCO Control Voltage (Pin12)

6.2

V

V

Vcog

VCO Gain (Pin 12)

17

kHz/V

Hph

Horizontal Phase Adjustment

% of Horizontal Period

±10

%

Hphmin

Hphtyp

Hphmax

Horizontal Phase Decoupling Output

Minimum Value

Typical Value

Maximum Value

Sub-Address 01, Pin 14

Byte x1111111

Byte x1000000

Byte x0000000

2.8

3.4

4.0

V

V

V

Free Running Frequency

22.3

kHz

dF0/dT

Free Running Frequency Thermal Drift

(No drift on external components)

-150

ppm/C

CR

PLL1 Capture Range

100

23.5

kHz

kHz

PLLinh

PLL1 Inhibition (Pin3)

Typ Threshold = 1.6V

PLL ON

PLL OFF

2

0.8

V

V

SFF

Safe Forced Frequency

SF1 Byte 11xxxxxx

SF2 Byte 10xxxxxx

Sub-Address 02

2F0

3F0

FC1

FC2

VCO Sawtooth Level

Pin 9 To filter

Pin 8 To filter

6.4

1.6

V

V

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth

Flyback Input Threshold Voltage (Pin 6)

0.65

0.75

V

Hjit

Horizontal Jitter (see Pins 8-9 filtering)

TBD

ppm

Horizontal Drive Output Duty-Cycle

(Pin 20 or 21) (see Note 1)

48

%

XRAYth

X-RAY Protection Input Threshold Voltage

Pin 15

8

V

Vphi2

Internal Clamping Levels on 2nd PLL Loop

Filter (Pin 4)

Low Level

High Level

1.6

4.0

V

V

VSCinh

Threshold Voltage To Stop H-Out,V-Out

Pin 18

7.5

V

IHblk

Maximum Horizont al Blanking Output

Current

10

mA

VHblk

Horizont al Blanking Output Low Level

(Blanking ON)

0.25

0.5

V

HDvd

HDem

Horizontal Drive Output

Low Level (Pin 20 to GND)

9.5

1.1

10

1.7

V

V

Notes : 1. Duty Cycle is the ratio of power transistor OFF time to period. Power transistor is OFF when output transistor is OFF.

2. Initial Condition for Safe Operation Start Up (Max. duty cycle).

TDA9106A

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