HORIZONTAL SECTION (continued)

Symbol

Parameter

Test Conditions

Min.

Typ. Max.

Unit

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth

Flyback Input Threshold Voltage (Pin 12)

0.65

0.75

V

Hjit

Horizontal Jitter

At 31.4kHz

70

ppm

HD

Horizontal Drive Output Duty-Cycle

Pin 26, see Note 7

48

%

XRAYth

X-RAY Protection Input Threshold Voltage

Pin 25, see Note 8

8

V

Vphi2

Internal Clamping Levels on 2nd PLL

Loop Filter (Pin 4)

Low Level

High Level

1.6

4.0

V

V

VSCinh

Threshold Voltage to Stop H-Out,V-Out,

B-Out and Reset XRAY

Pin 29

7.5

V

HDvd

Horizontal Drive Output (low level)

0.4

V

HORIZONTAL DYNAMIC FOCUS FUNCTION

HDFst

Horizontal Dynamic Focus Sawtooth

Minimum Level

Maximum Level

Pin 9, capacitor on

HFOCUSCAP and C0 = 820pF,

µs

2

4.7

V

V

HDFdis

Horizontal Dynamic Focus Sawtooth

Discharge Width

Start by HFLY center

400

ns

HDFDC

Bottom DC Output Level

Ω, Pin 10

2

V

TDHDF

DC Output Voltage Thermal Drift

(see Note 5)

200

ppm/C

HDFamp

Horizontal Dynamic Focus Amplitude

Min Byte xxx11111

Typ Byte xxx10000

Max Byte xxx00000

Sub-Address 03, Pin 10,

1

1.5

3

HDFKeyst

Horizontal Dynamic Focus Symmetry

Min A/B Byte xxx11111

Typ Byte xxx10000

Max A/B Byte xxx00000

Typ. Amp

B/A

A/B

A/B

2

2

3.5

1.0

3.5

VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola)

AMPVDF

Vertical Dynamic Focus Parabola (added

to horizontal) Amplitude with VAMP and

VPOS Typical

Min. Byte 000000

Typ. Byte 100000

Max. Byte 111111

Sub-Address 0F

0

0.5

1

VDFAMP

Parabola Amplitude Function of VAMP

(tracking between VAMP and VDF) with

VPOS Typ. (see Figure 1 and Note 9)

Sub-Address 05

Byte 10000000

Byte 11000000

Byte 11111111

0.6

1

1.5

VHDFKeyt

Parabola Asymetry Function of VPOS

Control (tracking between VPOS and VDF)

with VAMP Max.

Sub-Address 06

Byte x0000000

Byte x1111111

0.52

0.52

Notes : 5. These parameters are not tested on each unit. They are measured during our internal qualification.

7. Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is controlled OFF when the

output transistor is OFF.

8. See Figure 14.

9. S and C correction are inhibited so the output sawtooth has a linear shape.

TDA9109/N

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