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CDC857 датащи(PDF) 3 Page - Texas Instruments |
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CDC857 датащи(HTML) 3 Page - Texas Instruments |
3 / 12 page CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SPECIAL TEST MODES INPUTS OUTPUTS COMMENTS VCC AVCC G CLK† Y Y FBOUT FBOUT COMMENTS ON 0 V L L Z Z Z Z Clock Mode ON 0 V L H Z Z Z Z Clock Mode ON 0 V H L L H L H Clock Mode ON 0 V H H H L H L Clock Mode ON UP‡ ↓§ LZ Z L H PLL Mode ON UP‡ ↓§ H Z Z H L PLL Mode † Only one signal shown for this differential input. ‡ AVCC ramped up after two (2) high-to-low transitions on G input & G being low. § At least two (2) high-to-low transitions during AVCC = 0. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AGND 17 Ground Analog ground. AGND provides the ground reference for the analog circuitry. AVCC 16 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (G = 0), the PLL is powered down. CLK CLK 13 14 I Clock input, CLK provides the clock signal to be distributed by the CDC857 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN FBIN 36 35 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. FBOUT FBOUT 32 33 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. G 37 I Output bank enable. G is the output enable for outputs Y and Y. When G is low outputs Y are disabled to a high-impedance state. When G is high, all outputs Y are enabled and switch at the same frequency as CLK. GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 Ground Ground VCC 4, 11, 12, 15, 21, 28, 34, 38, 45 Power Power supply Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9 3, 5, 10, 20, 22, 46, 44, 39, 29, 27 O Clock outputs. These outputs provide low-skew copies of CLK. Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9 2, 6, 9, 19, 23, 47, 43, 40, 30, 26 O Clock outputs. These outputs provide low-skew copies of CLK. |
Аналогичный номер детали - CDC857 |
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Аналогичное описание - CDC857 |
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