SN54ABT646A, SN74ABT646A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3STATE OUTPUTS

SCBS069H − JULY 1991 − REVISED MAY 2004

7

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 2)

SN74ABT646A

VCC = 5 V,

TA = 25°C

MIN

MAX

UNIT

MIN

MAX

MIN

MAX

fclock

Clock frequency

125

125

MHz

tw

Pulse duration, CLK high or low

4

4

ns

tsu

Setup time, A or B before CLKAB

↑ or CLKBA↑

3

3

ns

th

Hold time, A or B after CLKAB

↑ or CLKBA↑

0

0

ns

switching characteristics over recommended ranges of supply voltage and operating free-air

SN54ABT646A

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25°C

MIN

MAX

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

fmax

125

125

MHz

tPLH

CLKBA or CLKAB

A or B

2.2

4

5.1

2.2

6.7

ns

tPHL

CLKBA or CLKAB

A or B

1.7

4

5.1

1.2

6.7

ns

tPLH

A or B

B or A

1.5

3

4.3

1.5

5

ns

tPHL

A or B

B or A

1.5

3.3

4.6

1.5

5.6

ns

tPLH

SAB or SBA†

B or A

1.5

4

5.7

1.5

7.8

ns

tPHL

SAB or SBA†

B or A

1.5

3.6

4.9

1.5

6.2

ns

tPZH

OE

A or B

1.5

4.3

5.3

1.5

7

ns

tPZL

OE

A or B

3

5.8

8

3

10.5

ns

tPHZ

OE

A or B

1.5

3.5

5.8

1

7.3

ns

tPLZ

OE

A or B

1.5

3

4

1.5

5.7

ns

tPZH

DIR

A or B

1.5

4.5

5.7

1.5

7.3

ns

tPZL

DIR

A or B

2.5

6.5

9

2.5

11

ns

tPHZ

DIR

A or B

1.5

3.8

6.5

1

9

ns

tPLZ

DIR

A or B

1.5

3.8

4.7

1.2

6.7

ns

† These parameters are measured with the internal output state of the storage register opposite that of the bus input.