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TEA1771 датащи(PDF) 7 Page - NXP Semiconductors

номер детали TEA1771
подробное описание детали  GreenChip PC primary control IC
Download  25 Pages
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TEA1771 датащи(HTML) 7 Page - NXP Semiconductors

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TEA1771_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 February 2009
7 of 25
NXP Semiconductors
TEA1771
GreenChip PC primary control IC
The switch that is in series with the current source, charging LVIN via DM2, is opened
when the IC is in System failure mode (see the SUPPLY block in Figure 1). The IC
consumption slowly discharges the LVIN capacitor. When VLVIN has been discharged to
the level of VDECVCC and VDECPVCC, these nodes are also discharged. Eventually the
DECVCC voltage will drop below the UVLO level and the IC enters Charge mode. This is
called a safe restart cycle. The period of this cycle depends on the capacitors at pins
LVIN, DECVCC, and DECPVCC.
8.4 Oscillator
In Figure 5 the OSCILLATOR block is shown together with the STANDBY block. The
OSCILLATOR block shows the internal capacitor that is subsequently charged and
discharged with the currents 0.3
× I
osc and 0.7 × Iosc. The lower part of Figure 5 shows the
oscillator signals. It points out that the Ich/Idch current ratio determines an internal clock
with a duty cycle of 0.7. In Section 8.5 will be made clear that the clock duty cycle
determines the max duty cycle that can be regulated.
Together with the capacitor value the Iosc current level determines the frequency. The Iosc
is not fixed and therefore the frequency varies also.
Figure 5 shows that Iosc is generated by the STANDBY block and fed to the
OSCILLATOR block. The curves in the STANDBY block show that Iosc is regulated by the
current on pin OPTO, IOPTO. For IOPTO >2IIREF the Iosc current is set to the maximum level,
Iosc =IIREF. As a result the frequency is set to the maximum level by putting IOPTO >2IIREF.
(1)
fosc(max) (kHz)
IIREF (µA)
IIREF is regulated by the external resistor to pin IREF. The voltage on this pin is set to
3.6 V. The current IIREF is set by choosing the resistor value.
(2)
Fig 4.
State diagram
014aaa172
CHARGE
RUNNING
VDECVCC < VUVLO(DECVCC)
SWP or OVP or
IOPTO > Iprot(OPTO)
SWP or OVP or
IOPTO > Iprot(OPTO)
VVRSTOK and
VLVIN > Vstartup(LVIN)
STATE DIAGRAM
SYSTEM FAILURE
f
osc max
()
I
IREF
2
-------------
=
I
IREF
V
IREF
R
IREF
---------------
3.6
R
IREF
--------------
==


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