поискавой системы для электроныых деталей |
|
TEA1771 датащи(PDF) 11 Page - NXP Semiconductors |
|
TEA1771 датащи(HTML) 11 Page - NXP Semiconductors |
11 / 25 page TEA1771_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 6 February 2009 11 of 25 NXP Semiconductors TEA1771 GreenChip PC primary control IC When the PSU is in Normal mode the duty cycle is independent of the operating frequency. The frequency is set to the maximum level and is proportional to IIREF. See Section 8.4. (6) • fosc(max) (kHz) • IIREF (µA) Figure 6 shows the sawtooth circuit. It also shows that the charge current of the Csaw capacitor is proportional to IIREF. Thus both the oscillation period, tosc, and the on-time, ton, are inverse proportional to IIREF. As a result the duty cycle, δ, is constant for varying operating frequencies. 8.6 Non-overlap times In the previous section the non overlap times ∆t1 and ∆t2 are introduced. In Figure 7 these times are illustrated. The delays, ∆t1 and ∆t2 avoid overlap in the on-time of the main switch and the reset switch. The delay ∆t1 is listed in the characteristics table: ∆t1=t no(rstsw-mainsw). The value slightly differs for Standby mode and Normal mode. In the characteristics table this is reflected by different delay values for a high and a low −I OPTO value that hold in Normal mode and Standby mode, respectively. The delay ∆t2 is less straightforward. It depends on the V DM1 signal. Figure 7 illustrates the mechanism showing stylized signals. When M1 is turned off the DM1 node is charged by the magnetizing current until it is clamped to the reset voltage. The primary controller waits for DM1 to be charged to the reset voltage before M2 is turned on. In fact, when this ramp has finished the controller waits an additional time, twait after which M2 is turned on. The DM1 voltage signal varies strongly as the PSU load is varied. By sensing the VDM1 ramp-up, hard switching of the reset switch is avoided in all load conditions. If (dV/dt)r is below detection level the VDM1 ramp-up is not sensed at all. In that case a delay is applied which, like ∆t1, is determined by the IC itself. This delay is called t no(bu), the backup delay. In Figure 7 this delay is illustrated by the dashed variant of M2. Counting time from the moment M1 is turned off M2 is turned after a delay of tno(bu) has passed. f osc max () I IREF 2 ------------- = Fig 7. ∆t2 non-overlap time between the main switch (mainsw) being turned off and the reset switch (rstw) being turned on. tramp twait M2 VDM1 Vrst M1 tno(bu) 014aaa727 |
Аналогичный номер детали - TEA1771 |
|
Аналогичное описание - TEA1771 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |