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SN74ACT8997 датащи(PDF) 6 Page - Texas Instruments

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номер детали SN74ACT8997
подробное описание детали  SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP CONCATENATORS
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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SN74ACT8997 датащи(HTML) 6 Page - Texas Instruments

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SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Test-Logic-Reset
In this state, the test logic is inactive and an internal reset signal is applied to all registers in the device. During
device operation, the TAP returns to this state in no more than five TCK cycles if the test mode select (TMS)
input is high. The TMS pin has an internal pullup that forces it to a high level if it is left unconnected or if a board
defect causes it to be open circuited. The device powers up in the Test-Logic-Reset state.
Run-Test /Idle
The TAP must pass through this state before executing any test operations. The TAP may retain this state
indefinitely, and no registers are modified while in Run-Test /Idle. The 8-bit programmable up/down counter can
be operated in this state.
Select-DR-Scan, Select-IR-Scan
No specific function is performed in these states; the TAP exits either of them on the next TCK cycle.
Capture-DR
The selected data register is placed in the scan path (i.e., between TDI and TDO). Depending on the current
instruction, data may or may not be loaded or captured by that register on the rising edge of TCK, causing the
TAP state to change.
Shift-DR
In this state, data is serially shifted through the selected data register from TDI to TDO on each TCK cycle. The
first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK
cycle in which the TAP changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). On the falling edge
of TCK in Shift-DR, TDO goes from the high-impedance state to the active state. TDO enables to the value
present in the least-significant bit of the selected data register.
Exit1-DR, Exit2-DR
These are temporary states that end the shifting process. It is possible to return to the Shift-DR state from either
Exit1-DR or Exit2-DR without recapturing the data register. The last shift occurs on the TCK cycle in which the
TAP state changes from Shift-DR to Exit-DR. TDO changes from the active state to the high-impedance state
on the falling edge of TCK in Exit1-DR.
Pause-DR
The TAP can remain in this state indefinitely. The Pause-DR state suspends and resumes shift operations
without loss of data.
Update-DR
If the current instruction calls for the latches in the selected data register to be updated with current data, the
latches are updated only during this state.
Capture-IR
The instruction register is preloaded with the IR status word (see Table 4) and placed in the scan path.
Shift-IR
In this state, data is serially shifted through the instruction register from TDI to TDO on each TCK cycle. The
first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK
cycle in which the TAP changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). On the falling edge of
TCK in Shift-IR, TDO goes from the high-impedance state to the active state, and will enable to a high level.


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