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SN74AS181AN датащи(PDF) 1 Page - Texas Instruments |
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SN74AS181AN датащи(HTML) 1 Page - Texas Instruments |
1 / 13 page SN54AS181B . . . JT OR JW PACKAGE SN74AS181A ...N OR NT PACKAGE (TOP VIEW) SN54AS181B . . . FK PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 B0 A0 S3 S2 S1 S0 Cn M F0 F1 F2 GND VCC A1 B1 A2 B2 A3 B3 G Cn + 4 P A = B F3 NC – No internal connection 32 1 28 27 12 13 5 6 7 8 9 10 11 25 24 23 22 21 20 19 A2 B2 A3 NC B3 G Cn + 4 S2 S1 S0 NC Cn M F0 426 14 15 16 17 18 SN54AS181B, SN74AS181A ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994 Copyright © 1994, Texas Instruments Incorporated 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 • Full Look Ahead for High-Speed Operations on Long Words • Arithmetic Operating Modes: – Addition – Subtraction – Shift Operand A One Position – Magnitude Comparison – Twelve Other Arithmetic Operations • Logic Function Modes: – Exclusive-OR – Comparator – AND, NAND, OR, NOR • Package Options Include Plastic Small-Outline (N) Packages, Ceramic (FK) Chip Carriers, Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs, and Ceramic (JW) 600-mil DIPs description The SN54AS181B and SN74AS181A arithmetic logic units (ALUs) / function generators have a complexity of 75 equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in Tables 1 and 2. These operations are selected by the four function-select (S0, S1, S2, and S3) lines and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries are enabled by applying a low-level voltage to the mode-control (M) input. A full carry look-ahead scheme is used to generate fast, simultaneous carry by means of two cascade (G and P) outputs for the four bits in the package. If high speed is not important, a ripple-carry (Cn) input and a ripple-carry (Cn + 4) output are available. The ripple-carry delay is minimized so that arithmetic manipulations for small word lengths can be performed without external circuitry. The SN54AS181B and SN74AS181A accommodate active-high or active-low data if the pin designations are interpreted as follows: PIN NUMBER 2 1 23 22 21 20 19 18 9 10 11 13 7 16 15 17 Active-low data (Table 1) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 Cn Cn + 4 P G Active-high data (Table 2) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 Cn Cn + 4 X Y Subtraction is accomplished by 1’s complement addition where the 1’s complement of the subtrahend is generated internally. The resultant output is A-B-1, which requires an end-around or forced carry to provide A-B. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Аналогичный номер детали - SN74AS181AN |
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Аналогичное описание - SN74AS181AN |
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