SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996

9

POST OFFICE BOX 655303

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

17

1OE

15

1A1

7

1Y1

16

2OE

14

1A2

6

1Y2

––

––

13

1A3

5

1Y3

––

––

12

1A4

4

1Y4

––

––

11

2A1

3

2Y1

––

––

10

2A2

2

2Y2

––

––

9

2A3

1

2Y3

––

––

8

2A4

0

2Y4

boundary-control register

The boundary-control register (BCR) is two bits long. The BCR is used in the context of the RUNT instruction

to implement additional test operations not included in the basic SCOPE

™ instruction set. Such operations

include PRPG and PSA. Table 3 shows the test operations that are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is

reset to the binary value 10, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.

TDO

TDI

Bit 0

(LSB)

Bit 1

(MSB)

Figure 3. Boundary-Control Register Order of Scan

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,

thereby reducing the number of bits per test pattern that must be applied to complete a test operation.

During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in

Figure 4.

Bit 0

TDO

TDI

Figure 4. Bypass Register Order of Scan

instruction-register opcode description

The instruction-register opcodes are shown in Table 2. The following descriptions detail the operation of

each instruction.