SN54GTL16923, SN74GTL16923

18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS

SCBS674E – AUGUST 1996 – REVISED NOVEMBER 1999

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR A OUTPUTS

S1

Open

GND

500

Ω

500

Ω

TEST

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

S1

Open

6 V

GND

tPLH

tPHL

3 V

VREF

VREF

VOH

VOL

3 V

tw

Input

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(CLKAB to B port)

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

(A port)

Timing

Input

Data Input

A port

Output

Input

VTT

Test

Point

CL = 30 pF

(see Note A)

From Output

Under Test

25

Ω

LOAD CIRCUIT FOR B OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(CLKBA to A port)

Data Input

B port

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

6 V

1.5 V

1.5 V

tPLH

tPHL

3 V

VOH

VOL

Input

Output

1.5 V

1.5 V

1.5 V

1.5 V

VTT

1.5 V

1.5 V

1.5 V

VREF

VREF

VOH

VOL

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

VOL + 0.3 V

VOH – 0.3 V

≈0 V

3 V

3 V

1.5 V

1.5 V

1.5 V

1.5 V

0 V

0 V

0 V

0 V

0 V

3 V

1.5 V

1.5 V

0 V

0 V

Figure 1. Load Circuits and Voltage Waveforms