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74LVTH16652DGGRE4 датащи(PDF) 2 Page - Texas Instruments |
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74LVTH16652DGGRE4 датащи(HTML) 2 Page - Texas Instruments |
2 / 13 page SN54LVTH16652, SN74LVTH16652 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS150K – JULY 1994 – REVISED APRIL 1999 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16652 is characterized for operation over the full military temperature range of –55 °C to 125°C. The SN74LVTH16652 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE INPUTS DATA I/O† OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8 OPERATION OR FUNCTION L H H or L H or L X X Input Input Isolation L H ↑↑ X X Input Input Store A and B data X H ↑ H or L X X Input Unspecified‡ Store A, hold B H H ↑↑ X‡ X Input Output Store A in both registers L X H or L ↑ X X Unspecified‡ Input Hold A, store B L L ↑↑ XX‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus and stored B data to A bus † The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. |
Аналогичный номер детали - 74LVTH16652DGGRE4 |
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Аналогичное описание - 74LVTH16652DGGRE4 |
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