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SN74ACT3641 датащи(PDF) 6 Page - Texas Instruments

номер детали SN74ACT3641
подробное описание детали  1024 횞 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
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SN74ACT3641 датащи(HTML) 6 Page - Texas Instruments

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SN74ACT3641
1024
× 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
W/RA
I
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high.
W/RB
I
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a
low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is low.
detailed description
reset
The SN74ACT3641 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A reset initializes the
memory read and write pointers and forces the IR flag low, the OR flag low, the AE flag low, and the AF flag high.
Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, its flag is set high
after at least two clock cycles to begin normal operation. A FIFO must be reset after power up before data is
written to its memory.
almost-empty flag and almost-full flag offset programming
Two registers in the SN74ACT3641 are used to hold the offset values for the AE and AF flags. The AE flag offset
register is labeled X, and the AF flag offset register is labeled Y. The offset registers can be loaded with a value
in three ways: one of two preset values are loaded into the offset registers, parallel load from port A, or serial
load. The offset register programming mode is chosen by the flag select (FS1, FS0) inputs during a low-to-high
transition on RST (see Table 1).
Table 1. Flag Programming
FS1
FS0
RST
X AND Y REGISTERS†
H
H
Serial load
H
L
64
L
H
8
L
L
Parallel load from port A
† X register holds the offset for AE; Y register holds the
offset for AF.
preset values
If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of a RST low-to-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high
transition of RST. After this reset is complete, IR is set high after two low-to-high transitions on CLKA. The first
two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset
register of the SN74ACT3641 uses port-A inputs (A9 – A0). Data input A9 is used as the most-significant bit of
the binary number. Each register value can be programmed from 1 to 1020. After both offset registers are
programmed from port A, subsequent FIFO writes store data in the SRAM.


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