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AD7846AQ датащи(PDF) 3 Page - Analog Devices

номер детали AD7846AQ
подробное описание детали  16-Bit Voltage Output DAC
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD7846AQ датащи(HTML) 3 Page - Analog Devices

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Parameter
Limit at TMIN to TMAX (All Versions)
Unit
Test Conditions/Comments
t1
0
ns min
R/
W to CS Setup Time
t2
60
ns min
CS Pulsewidth (Write Cycle)
t3
0
ns min
R/
W to CS Hold Time
t4
60
ns min
Data Setup Time
t5
0
ns min
Data Hold Time
t6
120
ns max
Data Access Time
t7
10
ns min
Bus Relinquish Time
60
ns max
t8
0
ns min
CLR Setup Time
t9
70
ns min
CLR Pulsewidth
t10
0
ns min
CLR Hold Time
t11
70
ns min
LDAC Pulsewidth
t12
130
ns min
CS Pulsewidth (Read Cycle)
NOTES
1Timing specifications are sample tested at +25
°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed
from a voltage level of 1.6 V.
2t
6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t
7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
AD7846
REV. E
–3–
Limit at
TMIN to TMAX
Parameter
(All Versions)
Unit
Test Conditions/Comments
Output Settling Time1
6
µs max
To 0.006% FSR. VOUT loaded. VREF– = 0 V. Typically 3.5
µs.
9
µs max
To 0.003% FSR. VOUT loaded. VREF– = –5 V. Typically 6.5
µs.
Slew Rate
7
V/
µs typ
Digital-to-Analog Glitch
Impulse
70
nV-secs typ
DAC alternately loaded with 10 . . . 0000 and
01 . . . 1111. VOUT unloaded.
AC Feedthrough
0.5
mV pk-pk typ
VREF– = 0 V, VREF+ = 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s.
Digital Feedthrough
10
nV-secs typ
DAC alternately loaded with all 1s and all 0s.
CS High.
Output Noise Voltage
Density 1 kHz–100 kHz
50
nV/
√Hz typ
Measured at VOUT. DAC loaded with 0111011 . . . 11.
VREF+ = VREF– = 0 V.
NOTES
1
LDAC = 0. Settling time does not include deglitching time of 2.5
µs (typ).
Specifications subject to change without notice.
TIMING CHARACTERISTICS (V
DD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V)
DATA
5V
t1
t3
t1
t3
t2
t12
t4
t5
t6
t7
DATA VALID
DATA VALID
t8
t9
t10
t9
t8
t9
t10
t11
LDAC
CLR
CS
R/
W
0V
5V
0V
5V
0V
5V
0V
5V
0V
Figure 3. Timing Diagram
Figure 2. Load Circuits for Bus Relinquish Time (t7)
b. VOL to High Z
a. VOH to High Z
b. High Z to VOL
a. High Z to VOH
Figure 1. Load Circuits for Access Time (t6)
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are not
subject to test. (VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = –14.25 V
to –15.75 V; VCC = +4.75 V to +5.25 V; RIN connected to 0 V.)
DBN
3k
100pF
DGND
DBN
100pF
3k
DGND
5V
DBN
3k
10pF
DGND
DBN
10pF
3k
DGND
5V


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