SN74ALVCH16901

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH PARITY GENERATORS/CHECKERS

SCES010E – JULY 1995 – REVISED FEBRUARY 1999

7

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figures 1 through 3)

VCC = 1.8 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

†

125

125

125

MHz

t

Pulse

CLK

↑

†

3

3

3

ns

tw

duration

LE high

†

3

3

3

ns

A, APAR or B, BPAR before CLK

↑

†

1.9

2

1.7

tsu

Setup time

CLKEN before CLK

↑

†

2.1

2.1

1.7

ns

A, APAR or B, BPAR before LE

↓

†

1.4

1.3

1.2

A, APAR or B, BPAR after CLK

↑

†

0.4

0.4

0.5

th

Hold time

CLKEN after CLK

↑

†

0.5

0.5

0.7

ns

A, APAR or B, BPAR after LE

↓

†

0.9

1.1

0.9

† This information was not available at the time of publication.