SN74F2373

25-

Ω OCTAL TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SDFS100 – JANUARY 1996

5

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

Test

Point

R1

CL

(see Note A)

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

LOAD CIRCUIT FOR

3-STATE AND OPEN-COLLECTOR OUTPUTS

R1

S1

7 V (tPZL, tPLZ, O.C.)

Open

(all others)

From Output

Under Test

Test

Point

R2

CL

(see Note A)

RL = R1 = R2

1.5 V

1.5 V

1.5 V

3 V

3 V

0 V

0 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing Input

(see Note C)

Data Input

(see Note C)

1.5 V

1.5 V

3 V

3 V

0 V

0 V

High-Level

Pulse

(see Note C)

Low-Level

Pulse

tw

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V

1.5 V

tPHL

tPLH

tPLH

tPHL

Input

(see Note C)

Out-of-Phase

Output

(see Note E)

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

3 V

0 V

VOL

VOH

VOL

In-Phase

Output

(see Note E)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (see Note D)

tPHZ

tPLZ

0.3 V

tPZL

tPZH

1.5 V

1.5 V

1.5 V

3 V

0 V

Output

Control

(low-level enable)

Waveform 2

(see Notes B and E)

0 V

VOH

VOL

3.5 V

0.3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

Waveform 1

(see Notes B and E)

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 1 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.

D. When measuring propagation delay times of 3-state outputs, switch S1 is open.

E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms