SN74FB2041A

7-BIT TTL/BTL TRANSCEIVER

SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002

7

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR A OUTPUTS

S1

500

Ω

500

Ω

From Output

Under Test

LOAD CIRCUIT FOR B OUTPUTS

2.1 V

16.5

Ω

CL = 30 pF

(see Note A)

Test

Point

tPHL

tPLH

Output

3 V

0 V

VOH

VOL

tPHL

tPLH

2 V

1 V

VOH

VOL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (B TO A)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (A TO B)

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPLZ

tPZH

tPZL

tPHZ

3.5 V

0 V

VOL + 0.3 V

VOH – 0.3 V

≈0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES (A PORT)

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,

tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

7 V

Open

Input

1.5 V

1.5 V

1.55 V

1.55 V

Output

Input

1.5 V

1.5 V

1.55 V

1.55 V

1.5 V

1.5 V

1.5 V

1.5 V

Figure 1. Load Circuits and Voltage Waveforms