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SN74GTLPH16612DGG датащи(PDF) 2 Page - Texas Instruments

номер детали SN74GTLPH16612DGG
подробное описание детали  18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is
a 16-slot, 14-inch board with loaded impedance of 33
Ω. VTT is 1.5 V, VREF is 1 V, and RTT pullup resistor is 50 Ω.
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot 1 signals are
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing
between receiver cards is reduced. The clock is independent of the data and the system clock frequency is
limited by the backplane flight time to about 80 MHz to 90 MHz. This frequency can be increased even more
(30% to 40%) if the clock is generated and transmitted together with the data from the driver card (source
synchronous).
The SN74GTLPH16612 is a medium-drive (34 mA), 18-bit universal bus transceiver, containing D-type latches
and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. This UBT
can replace any of the functions shown in Table 1.
Table 1. SN74GTLPH16612 UBT Replacement Functions
FUNCTION
8 BIT
9 BIT
10 BIT
16 BIT
18 BIT
Transceiver
’245, ’623, ’645
’863
’861
’16245, ’16623
’16863
Buffer/driver
’241, ’244, ’541
’827
’16241, ’16244, ’16541
’16825
Latched transceiver
’543
’16543
’16472
Latch
’373, ’573
’843
’841
’16373
’16843
Registered transceiver
’646, ’652
’16646, ’16652
’16474
Flip-flop
’374, ’574
’821
’16374
Standard UBT
’16500, ’16501
Universal bus driver
’16835
Registered transceiver with CLK enable
’2952
’16470, ’16952
Flip-flop with CLK enable
’377
’823
’16823
Standard UBT with CLK enable
’16600, ’16601
SN74GTLPH16612 UBT replaces all above functions
GTLP is a TI derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The ac specification
of the SN74GTLPH16612 is given only at the preferred higher noise-margin GTLP, but this device can be used
at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.
The B port normally operates at GTLP levels, while the A-port and control inputs are compatible with LVTTL
logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port.
To improve signal integrity, the SN74GTLPH16612 B-port output transition time is optimized for distributed
backplane loads.
VCC (5 V) supplies the internal and GTLP circuitry, while VCC (3.3 V) supplies the LVTTL output buffers.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74GTLPH16612 is characterized for operation from –40
°C to 85°C.


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