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TL16C752BPTRG4 датащи(PDF) 2 Page - Texas Instruments |
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TL16C752BPTRG4 датащи(HTML) 2 Page - Texas Instruments |
2 / 36 page TL16C752B 3.3-V DUAL UART WITH 64-BYTE FIFO SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description The TL16C752B is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics. The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities. The TL16C752B is available in a 48-pin PT (LQFP) package. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION A0 28 I Address 0 select bit. Internal registers address selection A1 27 I Address 1 select bit. Internal registers address selection A2 26 I Address 2 select bit. Internal registers address selection CDA, CDB 40, 16 I Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). CSA, CSB 10, 11 I Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C752B for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a low on the respective CS A and CS B pins. CTSA, CTSB 38, 23 I Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the 752B. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. D0–D4 D5–D7 44–48, 1–3 I/O Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. DSRA, DSRB 39, 20 I Data set ready (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR) DTRA, DTRB 34, 35 O Data terminal ready (active low). These outputs are associated with individual UART channels A and B. A logic low on these pins indicates that the 752B is powered on and ready. These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset. GND 17 Pwr Signal and power ground INTA, INTB 30, 29 O Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space or when a modem status flag is detected. INTA–B are in the high-impedance state after reset. IOR 19 I Read input (active low strobe). A high to low transition on IOR will load the contents of an internal register defined by address bits A0–A2 onto the TL16C752B data bus (D0–D7) for access by an external CPU. |
Аналогичный номер детали - TL16C752BPTRG4 |
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Аналогичное описание - TL16C752BPTRG4 |
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