поискавой системы для электроныых деталей |
|
TP3056BN датащи(PDF) 10 Page - Texas Instruments |
|
TP3056BN датащи(HTML) 10 Page - Texas Instruments |
10 / 19 page TP3056B MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of operating conditions (see Figures 1 and 2) MIN NOM MAX UNIT fclock(M) Frequency of master clock MCLK 2.048 MHz fclock(B) Frequency of bit clock, transmit BCLK 64 2048 kHz tw1 Pulse duration, MCLK high 160 ns tw2 Pulse duration, MCLK low 160 ns tr1 Rise time of master clock (20% to 80%) MCLK 50 ns tf1 Fall time of master clock (80% to 20%) MCLK 50 ns tr2 Rise time of bit clock (20% to 80%), transmit BCLK 50 ns tf2 Fall time of bit clock (80% to 20%), transmit BCLK 50 ns tsu1 Setup time, BCLK high (and FSX in long-frame sync mode) before MCLK ↓ (first bit clock after the leading edge of FSX) 100 ns tw3 Pulse duration, BCLK high, VIH = 2.2 V 160 ns tw4 Pulse duration, BCLK low, VIL = 0.6 V 160 ns th1 Hold time, FSX or FSR low after BCLK low (long frame only) 0 ns th2 Hold time, BCLK high after FSX or FSR ↑ (short frame only) 0 ns tsu2 Setup time, FSX or FSR high before BCLK ↓ (long frame only) 80 ns tsu3 Setup time, DR valid before BCLK ↓ 50 ns th3 Hold time, DR valid after BCLK ↓ 50 ns tsu4 Setup time, FSX or FSR high before BCLK ↓, short-frame sync pulse (1 or 2 bit-clock periods long) (see Note 7) 50 ns th4 Hold time, FSX or FSR high after BCLK ↓, short-frame sync pulse (1 or 2 bit-clock periods long) (see Note 7) 100 ns th5 Hold time, FSX or FSR high after BCLK ↓, long-frame sync pulse (from 3 to 8 bit-clock periods long) 100 ns tw5 Minimum pulse duration of FSX or FSR (frame sync pulse — low level), 64-kbps operating mode 160 ns NOTE 7: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high. switching characteristics over recommended ranges of operating conditions (see Figures 1 and 2) PARAMETER TEST CONDITIONS MIN MAX UNIT td1 Delay time, BCLK high to data valid at DX Load = 150 pF plus 2 LSTTL loads† 0 140 ns td2 Delay time, BCLK high to TSX low Load = 150 pF plus 2 LSTTL loads† 140 ns td3 Delay time, BCLK (or 8 clock FSX in long frame only) low to data output (DX) disabled 50 165 ns td4 Delay time, FSX or BCLK high to data valid at DX (long frame only) CL = 0 pF to 150 pF 20 165 ns † Nominal input value for an LSTTL load is 18 k Ω. |
Аналогичный номер детали - TP3056BN |
|
Аналогичное описание - TP3056BN |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |