TSB21LV03C

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS331A – FEBRUARY 1999 – REVISED OCTOBER 1999

8

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

NAME

NO.

TYPE

I/O

DESCRIPTION

NAME

HV

PM

ISO

7

62

CMOS

I

Link interface isolation input. ISO is normally tied high both to implement TI

bus-holder isolation or no isolation. The TSB21LV03C does not support Annex J

isolation.

LPS

11

2

CMOS

I

Link power status. LPS is connected to either the VDD supplying the LLC through

a 1–k

Ω resistor or directly to a pulsed output that is active when the LLC is

powered for the purpose of monitoring the LLC power status. The pulsed signal

must be between 220 kHz and 5.5 MHz to be sensed as active. If LPS is inactive,

the phy-LLC interface is disabled, and the TSB21LV03C performs only the basic

repeater functions required for network initialization and operation. LPS is 5-V

tolerant and has an internal bus-holder function built-in. If this terminal is tied

through a resistor to a fixed state, the resistor must be 1 k

Ω or less.

LREQ

12

3

CMOS

I

Link request. LREQ is an input from the LLC that requests the TSB21LV03C to

perform some service. LREQ is 5-V tolerant and has an internal bus-holder

function built-in. If this terminal is tied through a resistor to a fixed state, the

resistor must be 1 k

Ω or less.

PC2 – PC0

39, 40, 41

28, 29, 30

CMOS

I

Power class indicators. The PC signals set the bit values of the three

power-class bits in the Self-ID packet (bits 21, 22, and 23). These bits can be

programmed by tying the terminals to VDD (high) or to GND (low).

PD

16

7

CMOS

I

Power down. When asserted high, PD turns off all internal circuitry except the

CNA monitor circuits that drive the CNA terminal. PD is 5-V tolerant. The PD

terminal may be tied directly to VDD or to DGND. If this terminal is tied through a

resistor to a fixed state, the resistor must be 1 k

Ω or less. The PD terminal has an

internal bus-holder function built in to it.

PLLGND

64, 65

52, 53

Supply

—

PLL circuit ground. The PLLGND terminals should be tied to the low-impedance

circuit-board ground plane. External to the device, AGND should be tied to

DGND and PLLGND.

PLLVDD

2

58

Supply

—

PLL circuit power. PLLVDD supplies power to the PLL portion of the device. It is

recommended that a combination of high-frequency decoupling capacitors be

connected

to

PLLVDD (i.e., paralleled 0.1 µF and 0.001 µF). Lower frequency 10-µF filtering

capacitors can also be used. The PLLVDD supply terminals are separated from

AVDD and DVDD internally in the device to provide noise isolation. The PLLVDD,

AVDD, and DVDD terminals should also be tied together to a power plane on the

circuit board. Individual filtering networks for each is recommended.

R0

R1

3

4

59

60

—

—

Current setting resistor. An internal reference voltage is applied to a resistor con-

nected between R0 and R1 to set the operating current and the cable driver out-

put current. A resistance of 6.3 k

Ω ±0.5% should be used to meet the IEEE

1394-1995 standard requirements for output voltage limits.

RESET

10

1

CMOS

I

Reset. When RESET is asserted low (active), a bus reset condition is set on the

active cable ports and the the internal logic is reset to the reset start state. An

internal pullup resistor, which is connected to VDD, is provided so only an exter-

nal delay capacitor is required. This input is a standard logic buffer and can also

be driven by an open-drain logic output buffer. The minimum hold time for RE-

SET is listed in the recommended operating characteristics table.

SYSCLK

19

9

CMOS

O

System clock. SYSCLK provides a 49.152-MHz clock signal, which is synchro-

nized with the data transfers to the LLC.

TESTM1

TESTM2

32

31

22

21

CMOS

I

Test mode control. TESTM1 and TESTM2 are used during the manufacturing

test and should be tied to VDD.