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STA2065N датащи(PDF) 5 Page - STMicroelectronics |
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STA2065N датащи(HTML) 5 Page - STMicroelectronics |
5 / 20 page STA2065 System description Doc ID16050 Rev 1 5/20 2 System description 2.1 MCU ARM1176-JZF advanced risc machine CPU up to 624 MHz (with Vdd greater or equal to 1.20 V and under process and temperature worst case conditions). 2.2 Embedded memories 2.2.1 Embedded SRAM (eSRAM) The embedded SRAM is 8K x 32 (32 KB). 2.3 System functions 2.3.1 System and reset controller (SRC) This provides a control interface for clock generation components external to the subsystem. It also controls system-wide and peripherals-specific energy management features. 2.3.2 PMU The power manager module controls the SLEEP to DEEP-SLEEP modes transition, controls the external voltage switches on the Vdd and Vddio, monitors the external power supply (via two signals, Vddok and BATOK), can force the emergency entry of the SDRAM in self-refresh, and controls the wake-up from DEEP-SLEEP mode. 2.3.3 DMA Direct memory access can be used with DMA peripherals. FIFO fill/empty requests from these peripherals can be serviced immediately by the DMA Controller without CPU interaction. Peripheral-to-peripheral and memory-to-memory DMA are also supported. STA2065 features two DMA engines. Each DMA supports up to 8-channels and up to 32 requests. 2.3.4 Vectored interrupt controller (VIC) The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in response to peripheral interrupts. 2.3.5 GPIOs Four GPIO ports provide 160 programmable inputs or outputs that can be controlled in two modes: ● software mode through an APB bus interface ● hardware mode through a hardware control interface |
Аналогичный номер детали - STA2065N |
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Аналогичное описание - STA2065N |
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