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TPS658620ZQZT датащи(PDF) 29 Page - Texas Instruments

номер детали TPS658620ZQZT
подробное описание детали  Advanced Power Management Unit
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производитель  TI [Texas Instruments]
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TPS658620ZQZT датащи(HTML) 29 Page - Texas Instruments

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3.7 I
2C COMMUNICATION PROTOCOL
TPS658620
Advanced Power Management Unit
www.ti.com
SLVS993 – OCTOBER 2009
The following conventions will be used when describing the communication protocol:
CONDITION
CODE
START sent from host
S
STOP sent from host
P
TPS658620 I2C slave address sent from host (WRITE)
hA0
TPS658620 register address sent from TPS658620 (READ)
hA1
Non-valid I2C slave address sent from host
hA_N
Valid TPS658620 register address sent from host
HCMD
Non-valid TPS658620 register address sent from host
HCMD_N
I/O data byte (8 bits) sent from host to TPS658620
hDATA
I/O data byte (8 bits) sent from TPS658620 to host
bqDATA
Acknowledge (ACK) from host
hA
Not acknowledge (NACK) from host
hN
Acknowledge (ACK) from TPS658620
bqA
Not acknowledge (NACK) from TPS658620
bqN
Figure 3-1. I2C Conditions
For normal data transfers, the data line (SDAT or PSDAT) is allowed to change only when the clock line
(SCLK or PSCLK) is low, and one clock pulse is used per bit of data. The data line must remain stable
whenever the clock line is high, as data changes when the clock is high are reserved for indicating the
start and stop conditions. Each data transfer is initiated with a start condition and terminated with a stop
condition.
When addressed, the TPS658620 device generates an acknowledge bit after the reception of each byte
by pulling the data line Low. The master device (microprocessor) must generate an extra clock pulse that
is associated with the acknowledge bit. After the acknowledge/not acknowledge bit, the TPS658620
leaves the data line high, enabling a STOP condition generation.
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DETAILED DESCRIPTION
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