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TPS658620ZQZT датащи(PDF) 32 Page - Texas Instruments

номер детали TPS658620ZQZT
подробное описание детали  Advanced Power Management Unit
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TPS658620ZQZT датащи(HTML) 32 Page - Texas Instruments

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3.14 INCREMENTAL READ (SDAT/SCLK ONLY)
3.15 I
2C COMMUNICATION PROTOCOL – POWER I2C INTERFACE, PINS PSDAT/PSCLK
3.16 SIMULTANEOUS STANDARD AND POWER I
2C OPERATION
TPS658620
Advanced Power Management Unit
SLVS993 – OCTOBER 2009
www.ti.com
Attempt to Specify Non-Allowed WRITE Address
If the host attempts to WRITE to a READ-ONLY or non-accessible address, the TPS658620 ACKS the
CMD containing the allowed READ address, loads the address into the address register and ACKS after
the host sends the next data byte. A subsequent hA1 READ could read this address, but the data sent by
the host will not have been written.
S
hA0
bqA
hCMD
bqA
hDATA
bqA
The SDAT/SCLK I2C interface supports incremental read operations. Each register must be accessed in a
single read operation. A valid WRITE address is required to write to the RAM, and a valid READ address
is required to specify the initial RAM address where the READ starts. Once a read command is received,
the RAM data for the specified address is output to the host. If the host chooses, it can loop through the
remaining addresses; the address is automatically incremented by one at the end of each read. If the loop
gets to the top address, it automatically rolls over to address 0x00 and the sequence stops.
The Power I2C interface is designed to support fast write operations using multiple register-data pair
sequences. The Power I2C engine is a write-only engine, and it does not support read operations.
During a write sequence, the host sends the start command, followed by the TPS658620 address. Then
the host sends the register address byte, followed by eight bits of the data for the respective register
(Register1 Address/Data in Figure 3-3). From this point on the TPS658620 will accept all the following 2
byte pairs as a random register address, followed by the data content to be written to that register. This
process continues until the host sends a valid stop condition after the last register (Register N in
Figure 3-3) is written. A typical multi-byte sequence is shown in Figure 3-3.
Figure 3-3. Power I2C Protocol
The TPS658620 has individual address pointers for the Power I2C engine and Standard I2C engine. The
value written to the register will be defined by the relative timing between read/write pulses when
simultaneous I2C read/write operations happen. Simultaneous write/read operations to the same register
will be handled as follows:
1. Both Standard I2C and Power I2C are executing operations accessing distinct registers at the same
time (simultaneous read/read, read/write, write/read or write/write): No conflict exists in this case.
2. Power I2C writes and Standard I2C reads the same register at the same time
a.
Standard I2C will read the old register value if the Standard I2C read pulse is generated at least
110nsec (typ) before the Power I2C write pulse happens.
b.
Standard I2C will read the new register value if the Standard I2C read pulse is generated at least
110nsec (typ) after the Power I2C write pulse happens.
3. Power I2C and Standard I2C write to the same register at the same time
DETAILED DESCRIPTION
32
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