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TPS658620ZQZT датащи(PDF) 48 Page - Texas Instruments

номер детали TPS658620ZQZT
подробное описание детали  Advanced Power Management Unit
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TPS658620
Advanced Power Management Unit
SLVS993 – OCTOBER 2009
www.ti.com
• HOTPLUG Timer (T
HOTPLUG): SLEEP REQUEST state set by V(SYS) < VLOWSYS is inhibited until this
timer expires
• NORTC Timer (T
NORTC): NORTC pin will be set to a logic low level until this timer expires
The BOOT timer value is set to 500ms and the NORTC pulse width is set to 10ms.
The I2C engines are available while the device is in the SUPPLYSEQ state, however write operations to
the DVM registers are disabled, refer to DVM register section for more details. The TPS658620 remains in
this state until all the supplies are sequenced and the internal delay TSYNCEND (5ms typ) has expired.
POWER GOOD CHECK: Supplies that were powered up during the SUPPLYSEQ state will have their
power good flags checked during the POWER GOOD CHECK state (with exception of RTC_OUT ldo).
The POWER GOOD CHECK state ends and the NORMAL state is set when a power good fault is not
present or if the host writes SETNORMAL to 1 (register 0x14, Bit B2). If a power good fault is detected,
the POWER GOOD CHECK state will move to the the SLEEP REQUEST state when the boot timer
expires.
NORMAL STATE: In this state write operations to the DVM registers are enabled and the external host
controls all the TPS658620 functions. The normal state operation ends if a fault condition (defined as
either a thermal fault, V(SYS) < VLOW_SYS or a supply power good fault) is detected or if hardware or
software commands trigger a sleep or reboot request. While in NORMAL mode, the host can mask any of
the power supply power good fault detection via I2C registers PGFLTMASK1 and PGFLTMASK2. Supplies
that have their power good fault detection masked will not end the normal state operation. However, the
status bit for the supply indicates that the output voltage is out of regulation. A RTC_OUT LDO power
good fault does not trigger a transition to SLEEP REQUEST.
Table 3-14. Sequencer Power Good Fault Masking
PGFLTMASK1 [Addr 0x4D]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
MASK_PLDO8
MASK_PLDO7
MASK_PLDO6
MASK_PLDO4
MASK_PLDO3
MASK_PLDO2
MASK_PLDO1
MASK_PLDO0
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
Function
PGOODLDO8
PGOODLDO7
PGOODLDO6
PGOODLDO4
PGOODLDO3
PGOODLDO2
PGOODLDO1
PGOODLDO0
When 0
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
When 1
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
PGFLTMASK2 [Addr 0x4E]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
MASK_PSM3
MASK_PSM2
MASK_PSM1
MASK_PSM0
MASK_PLDO9
MASK_PLDO5
RSVD4E1
RSVD4E0
MASK
MASK
MASK
MASK
MASK
MASK
Function
NOT USED
NOT USED
PGOODSM3
PGOODSM2
PGOODSM1
PGOODSM0
PGOODLDO9
PGOODLDO5
When 0
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
NOT USED
NOT USED
When 1
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
NOT USED
NOT USED
SLEEP REQUEST: The SLEEP REQUEST state is set at anytime when a thermal fault condition is
detected. It is also set when the TPS658620 is in the NORMAL state followed by one of the events shown
below.
1. A hardware sleep request is detected at the RESUME pin.
2. A power good fault is detected at any of the integrated supplies
3. V(SYS_IN) < VLOW_SYS and the HOTPLUG timer has expired (t > THOTPLUG)
4. SLEEP MODE is 1 (register 0x14, bit B3)
When the SLEEP REQUEST state is set an internal timer is started and bit SLEEPREQ=1 is set in
register STAT3 (address 0xBB). Writing EXITSLREQ to 1 (0x14, bit B1) returns the TPS658620 to the
NORMAL state. If no action is taken by the host, while SLEEP_REQUEST state is set, the NOPOWER pin
is pulled low when TWAIT1 expires and the SLEEP state is entered after the TWAIT timer expires.
DETAILED DESCRIPTION
48
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