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TPS658620ZQZT датащи(PDF) 75 Page - Texas Instruments

номер детали TPS658620ZQZT
подробное описание детали  Advanced Power Management Unit
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производитель  TI [Texas Instruments]
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TPS658620
Advanced Power Management Unit
www.ti.com
SLVS993 – OCTOBER 2009
2. The maximum time for the address pointer to be in this range is 1 ms
3. Always read RTC_ALARM2 in the following order to prevent the address pointer from stopping at
0xC6: RTC_ALARM2_LO, then RTC_ALARM2_HI
When the RTC_OUT voltage falls below the internal RTC circuit Power On Reset threshold, VUVLO_RTC,
the RTC_CTRL register is reset. The host can identify this situation by reading the bit, POR_RESET_N,
which will be 0.
The clock selection is controlled by OSC_SRC_SEL (RTC_CTRL [6]). The internal 32kHz oscillator is
connected to the RTC when the OSC_SRC_SEL bit is reset. Once the processor is running, the software
can set this bit to 1, thereby connecting the 32.768 kHz crystal oscillator clock to the RTC. After being set,
the OSC_SRC_SEL bit will remain 1 selecting the crystal oscillator clock, as long as the VRTC_OUT
voltage
remains
above
the
RTC_OUT
Power
On
Reset
threshold.
POR_RESET_N=HI
when
OSC_SRC_SEL is set HI, indicating to the host that the crystal clock is being delivered to the RTC.
The RTC_ENABLE (RTC_CTRL [5]) bit is cleared to 0 by the RTC_OUT Power On Reset, disabling the
RTC counter. To enable incrementing of the RTC_COUNT [39:0] from an initial value set by the host, the
RTC_ENABLE bit should be written to 1 only after the RTC_OUT voltage reaches the operating range.
The RTC_ENABLE bit must be cleared to 0 before any new value is written to the RTC_COUNT register.
Table 3-52. RTC Control(1)
RTC_CTRL [Addr 0xC0]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
POR_RESET_N
OSC_SRC_SEL
RTC_ENABLE
BUF_ENABLE
PRE_BYPASS
CL_SEL[1]
CL_SEL[0]
RSVDC00
Function
RESET RTC
32K CLOCK
RTC COUNTER
32KHZ BUFFER
RTC COUNTER
INTERNAL XTAL1,
PIN
RTC_ALARM2
COUNTER
SELECTION
CLOCK AND
ENABLE
SCALING
XTAL2
CAPACITANCE
DETECTION
ALARM1/2
EXITS SLEEP
When 0
RESET RTC
INTERNAL 32K
DISABLED
DISABLED
USE 32K/32
SEE CL_SEL SETTINGS TABLE
DISABLED
COUNTER
When 1
OSC_SRC_SEL BIT =
CRYSTAL 32K
ENABLED
ENABLED
USE 32K
SEE CL_SEL SETTINGS TABLE
ENABLED
1
(1)
B7 is READ ONLY, all other bits have Read/Write access
The selected 32KHz clock is applied to a prescaler that can divide it by 32, resulting in a timer tick
resolution of either 32,768 ticks per second (pre-scaler disabled, PRE_BYPASS is 1) or 1,024 ticks per
second (pre-scaler enabled, PRE_BYPASS is 0). The 32,768 Hz or 1024 Hz clock increments a 40 bit
counter that tracks the real time and which can be read at anytime via I2C. With the prescaler enabled, the
RTC count has a range of approximately 34 years. The RTC counter and alarm registers are shown
below, the 40 bit RTC Counter is cleared only on when RTC_OUT is below the UVLO threshold.
Table 3-53. RTC Counter
RTC_COUNT4 [Addr 0xC6]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RTC[39]
RTC[38]
RTC[37]
RTC[36]
RTC[35]
RTC[34]
RTC[33]
RTC[32]
RTC_COUNT3 [Addr 0xC7]
Default to 0
Bit Name
RTC[31]
RTC[30]
RTC[29]
RTC[28]
RTC[27]
RTC[26]
RTC[25]
RTC[24]
RTC_COUNT2 [Addr 0xC8]
Default to 0
Bit Name
RTC[23]
RTC[22]
RTC[21]
RTC[20]
RTC[19]
RTC[18]
RTC[17]
RTC[16]
RTC_COUNT1 [Addr 0xC9]
Default to 0
Bit Name
RTC[15]
RTC[14]
RTC[13]
RTC[12]
RTC[11]
RTC[10]
RTC[9]
RTC[8]
RTC_COUNT0 [Addr 0xCA]
Default to 0
Bit Name
RTC[7]
RTC[6]
RTC[5]
RTC[4]
RTC[3]
RTC[2]
RTC[1]
RTC[0]
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DETAILED DESCRIPTION
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