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TPS658620ZQZT датащи(PDF) 81 Page - Texas Instruments

номер детали TPS658620ZQZT
подробное описание детали  Advanced Power Management Unit
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3.62.5 EXTERNAL TRIGGER SETUP
TPS658620
Advanced Power Management Unit
www.ti.com
SLVS993 – OCTOBER 2009
Table 3-64. ADC0 Conversion Wait Settings (Default in BOLD);
Valid for All Timing Engines
WAIT0[3:0]
WAIT TIME (ms)
WAIT0[3:0]
WAIT TIME (ms)
0000
0.000
1000
8.000
0001
0.062
1001
16.00
0010
0.125
1010
32.00
0011
0.250
1011
64.00
0100
0.500
1100
128.0
0101
1.000
1101
256.0
0110
2.000
1110
512.0
0111
4.000
1111
1024
The ADC conversion cycle can be started via an internal or external trigger when using the ADC0 timing
engine. The trigger is selectable by setting bits ADC0_TRIG4, ADC0_TRIG2 in registers ADC0_DELAY.
Table 3-65. Trigger Settings
ADC0_DELAY [Addr 0x67]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
ADC0_TRIG4
ADC0_TRIG2
ADC0HOLD
ADC0_EDGE
RSVD673
DELAY0[2]
DELAY0[1]
DELAY0[0]
Function
GPIO4 IS ADC0
GPIO2 IS ADC0
ADC HOLDOFF
NOT USED
NOT USED
ADC EXTERNAL TRIGGER DELAY (
µs)
EXT TRIGGER
EXT TRIGGER
ON/OFF CONTROL
When 0
DISABLED
DISABLED
OFF
NOT USED
NOT USED
000=00 001=50 010= 100 011=150
100=200 101=250 110=350 111=450
When 1
ENABLED
ENABLED
ON
NOT USED
NOT USED
When more than one GPIO trigger source is selected the GPIO signals are OR'ed prior to trigger
detection. When both of those bits are cleared to 0 the internal trigger is selected.
ADC0_HOLDOFF (ADC0_DELAY[5]) enables the GPIOx trigger source to be used as a level-sensed
gating signal which will suspend conversion cycles when the trigger source is low. The default for this bit
is 0. When ADC0HOLD is 0, the conversion cycle will continue for the preset number of conversions
selected with the RD_MODE bits once the initial trigger occurs. If the ADC0HOLD bit is 1, any pending
conversion cycle can be suspended if the GPIO trigger goes low (and resumes once the trigger signal
goes high again and the trigger delay time has been met). ADC0_DELAY[2:0] are used to set the initial
wait interval from the trigger event until the first conversion in a cycle is started. This delay may be from 0
to 450
µs.
When the GPIO's are selected as external triggers the ADC conversion start will be dependent on the
GPIO configuration. Table 3-66 shows the possible options:
Submit Documentation Feedback
DETAILED DESCRIPTION
81


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