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TPS658621A датащи(PDF) 82 Page - Texas Instruments

номер детали TPS658621A
подробное описание детали  Advanced Power Management Unit
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TPS658621A
SLVSA58 – DECEMBER 2009
www.ti.com
Table 3-62. ADC Channel Select Settings (Default in bold) (continued)
CHSELn[3:0]
CHANNEL
CHSELn[3:0]
CHANNEL
0101
CH6
1101
AGND
0110
CH7
1110
AGND
0111
CH8
1111
AGND
Continuous sampling mode can be set by writing REPEAT to 1 and RD0_MODE[1:0]=00. With those
settings the conversions will be performed as single samples, without wait times, until the ADC_EN bit is
cleared by the host or a limit violation occurs. If fixed-interval sampling mode (REPEAT0 = 0) is chosen,
the conversion cycle will consist of a specific number of samples (1, 16, 32, or 64) as specified by the
RD0_MODE[1:0] bits. When a multiple sample conversion cycle is selected the time interval between
individual samples is defined by the WAIT bits (register ADC0_WAIT). To exit the continuous conversion
mode before a limit violation occurs, the host must first set the REPEAT bit to LO, and then set the
ADC0_EN bit to 0.
3.62.4 Timing and ADC Reference Setup
The ADC0_WAIT register controls the ADC0 timing engine reset, wait time value and the converter
internal reference voltage enable. The ADC reference and SAR are disabled when AUTO_REF=0 AND
REF_EN=0. The use of external references for the ADC is not supported.
Table 3-63. ADC0 Conversion Timing
ADC0_WAIT [Addr 0x62]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
ADC_RESET
RSVD626
AUTO_REF
REF_EN
WAIT0[3]
WAIT0[2]
WAIT0[1]
WAIT0[0]
RESET
WAIT TIME BETWEEN INDIVIDUAL CONVERSIONS,
Function
CONVERSION
NOT USED
ADC Conversion Control
REPEAT MODE ENABLED (ms)
CYCLE
ALL ADC
When 0
ENGINES
NOT USED
Function is based on ADC
ACTIVE
SEE WAIT0 SETTINGS TABLE
Conversion Control
RESET ALL
When 1
NOT USED
ADC ENGINES
Table 3-64. ADC Conversion Control
(Default in bold)
AUTO_REF
REF_EN
DESCRIPTION
0
0
Reference and ADC disabled
0
1
Manual control of the Reference. WAIT=0 is not valid. 8ms must occur between REF_EN=1 and ADC0_EN=1
1
0
Automatic control of the Reference. Automatically enabled 8 ms before an ADC conversion is started.
1
1
Not a valid state
The relative timing between enabling the internal ADC reference / ANLGn pin bias currents and the start
of a conversion cycle is controlled by bits AUTO_REF and REF_EN. Those bits allow implementation of a
software only reference enable control or automatic reference enable control, as shown below:
Software enables ADC reference: Clear AUTO_REF bit to 0. Software must set REF_EN to 1 at least 8
ms before enabling an ADC engine and not clear REF_EN until all ADC engines are stopped.
Automatic ADC reference enable, internal or external trigger, wait time < 8ms : Set AUTO_REF bit to
1. The ADC logic will keep the ADC reference always on.
Automatic ADC reference enable, internal trigger, wait time > 8ms : Set AUTO_REF bit to 1. The ADC
logic enables the ADC reference 8 ms before the programmed wait time is reached
82
DETAILED DESCRIPTION
Copyright © 2009, Texas Instruments Incorporated
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