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TPS658621AZGUR датащи(PDF) 31 Page - Texas Instruments |
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TPS658621AZGUR датащи(HTML) 31 Page - Texas Instruments |
31 / 105 page TPS658621A www.ti.com SLVSA58 – DECEMBER 2009 2. TPS658621A ACK’s that this is a valid I2C address and that the bus is configured for write 3. Host sends TPS658621A register address 4. TPS658621A ACK’s that this is a valid register and stores the register address to be read 5. Host sends a repeated start and TPS658621A I2C slave address, reconfiguring the bus for read 6. TPS658621A ACK’s that this is a valid address and that bus is reconfigured 7. Bus is in read mode, TPS658621A starts sending data from selected register The I2C write protocol is similar to the read, without the need for a repeated start and bus being set in write mode. In a WRITE, it is not necessary to end each 1 byte WRITE command with a STOP as a START will have the same effect (repeated start). The host can complete a READ or a WRITE sequence with either a STOP or a START. NOTE Read operations are not supported for the PSDAT/PSCLK I 2C engine. Figure 3-2. I2C Read/Write Example 3.9 VALID WRITE SEQUENCES (SDAT/SCLK, PSDAT/PSCLK) The TPS658621A will always ACK its own address. If CMD points to an allowable READ or WRITE address, the device writes the address into its RAM address register and sends an ACK. If CMD points to a non-allowed address, the device does NOT write the address into its RAM address register and sends a NACK. Copyright © 2009, Texas Instruments Incorporated DETAILED DESCRIPTION 31 Submit Documentation Feedback Product Folder Link(s): TPS658621A |
Аналогичный номер детали - TPS658621AZGUR |
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Аналогичное описание - TPS658621AZGUR |
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