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TDA8029C1 датащи(PDF) 11 Page - NXP Semiconductors |
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TDA8029C1 датащи(HTML) 11 Page - NXP Semiconductors |
11 / 59 page 9397 750 14145 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 22 February 2005 11 of 59 Philips Semiconductors TDA8029 Low power single card reader Stop clock mode: The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and special function registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power-down mode is suggested. Idle mode: In the Idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the Idle mode is the last instruction executed in the normal operating mode before the Idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a Power-on reset. Power-down mode: To save even more power, a Power-down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power-down is the last instruction executed. Either a hardware reset, external interrupt or reception on RX can be used to exit from Power-down mode. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. With INT0_N, INT1_N or RX, the bits in register IE must be enabled. Within the INT0_N interrupt service routine, the controller has to read out the Hardware Status Register (HSR @ 0Fh) and/or the UART Status register (USR @ 0Eh) by means of MOVX-instructions in order to know the exact interrupt reason and to reset the interrupt source. For enabling a wake up by INT1_N, the bit ENINT1 within UCR2 must be set. For enabling a wake up by RX, the bits ENINT1 and ENRX within UCR2 must be set. An integrated delay counter maintains internally INT0_N and INT1_N LOW long enough to allow the oscillator to restart properly, so a falling edge on pins RX, INT0_N and INT1_N is enough for awaking the whole circuit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into power-down. 8.2 Timer 2 operation Timer 2 is a 16-bit timer and counter which can operate as either an event timer or an event counter, as selected by bit C/T2 in the special function register T2CON. Timer 2 has three operating modes: capture, auto-reload (up- or down counting), and baud rate generator, which are selected by bits in register T2CON. Table 6: External pin status during Idle and Power-down mode Mode Program memory ALE PSEN_N Port 0 Port 1 Port 2 Port 3 Idle internal 1 1 data data data data Idle external 1 1 float data address data Power-down internal 0 0 data data data data Power-down external 0 0 float data data data |
Аналогичный номер детали - TDA8029C1 |
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Аналогичное описание - TDA8029C1 |
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