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FAN4800IM датащи(PDF) 11 Page - Fairchild Semiconductor |
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FAN4800IM датащи(HTML) 11 Page - Fairchild Semiconductor |
11 / 20 page © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev. 1.0.5 11 Figure 7. PFC Section Block Diagram 1.6 Error Amplifier Compensation The PWM loading of the PFC can be modeled as a neg- ative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 8 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current-loop compensation is returned to VREF to pro- duce a soft-start characteristic on the PFC: As the refer- ence voltage increases from 0V, it creates a differentiated voltage on IEAO, which prevents the PFC from immediately demanding a full duty cycle on its boost converter. 1.7 PFC Voltage Loop There are two major concerns when compensating the voltage loop error amplifier (VEAO); stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency half that of the line fre- quency, or 23Hz for a 47Hz line (lowest anticipated inter- national power frequency). The gain vs. input voltage of the FAN4800’s voltage error amplifier (VEAO) has a spe- cially shaped non-linearity, so that under steady-state operating conditions, the transconductance of the error amplifier is at a local minimum. Rapid perturbation in line or load conditions causes the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier increases significantly, as shown in the Figure 4. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with conventional linear gain characteristics. The Voltage loop gain(s) is given by: where: ZC: Compensation network for the voltage loop. GMV: Transconductance of VEAO. PIN: Average PFC input power. V2OUTDC: PFC boost output voltage (typical designed value is 380V). CDC: PFC boost output capacitor. 1.8 PFC Current Loop The compensation of the current amplifier (IEAO) is simi- lar to that of the voltage error amplifier (VEAO) with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least ten times that of the voltage amplifier to prevent interaction with the voltage loop. It should also be limited to less than one sixth of the switching frequency, e.g., 16.7kHz for a 100kHz switching frequency. The current loop gain(s) is given by: RAMP1 OSCILLATOR 4 3 15 2 POWER FACTOR CORRECTOR GAIN MODULATOR V FB 7.5V REFERENCE 7 S R Q S R Q I EAO V EAO PFC OUT 2.78V -1V 12 14 0.3V Low Power Detector V CC TRI-FAULT V CC OVP PFC OVP PFC CMP CLK 13 1 16 3.5k 3.5k 2.5V I AC I SENSE V RMS 0.5V 17.9V PFC I LIMIT V CC V REF FAN4800 Rev.02 (6) OUT EAO FB EAO OUT FB IN VC OUTDC EAO DC VV V VV V PV GM Z VV S C 2 2.5 Δ Δ Δ =× × ΔΔ Δ × ≈× × ×Δ × × (7) ISENSE OFF EAO OFF EAO ISENSE OUTDC S ICI VD I DI V VR GM Z SL V 2.5 Δ ΔΔ =× × ΔΔ Δ × ≈× × ×× |
Аналогичный номер детали - FAN4800IM |
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Аналогичное описание - FAN4800IM |
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