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74AUP3G04 датащи(PDF) 1 Page - NXP Semiconductors |
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74AUP3G04 датащи(HTML) 1 Page - NXP Semiconductors |
1 / 17 page 1. General description The 74AUP3G04 provides a low-power, low-voltage triple inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114F Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101D exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78B Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C 74AUP3G04 Low-power triple inverter Rev. 03 — 8 October 2009 Product data sheet |
Аналогичный номер детали - 74AUP3G04 |
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Аналогичное описание - 74AUP3G04 |
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