74HC73DB datasheet(7/16 Pages) NXP

номер детали	74HC73DB

подробное описание детали	Dual JK flip-flop with reset; negative-edge trigger

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74HC73_4

Product data sheet

Rev. 04 — 19 March 2008

7 of 16

NXP Semiconductors

74HC73

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

[1]

tpd is the same as tPHL, tPLH.

[2]

tt is the same as tTHL, tTLH.

[3]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(C

L × VCC

2

× f

o) = sum of outputs.

th

hold time

nJ, nK to nCP; see Figure 6

VCC = 2.0 V

3

−8-

3

-

ns

VCC = 4.5 V

3

−3-

3

-

3

-

ns

VCC = 6.0 V

3

−2-

3

-

3

ns

fmax

maximum

frequency

nCP input; see Figure 6

VCC = 2.0 V

6.0

23

-

4.8

4.0

-

MHz

VCC = 4.5 V

30

70

-

24

-

20

-

MHz

VCC = 6.0 V

35

83

-

28

-

24

-

MHz

VCC = 5.0 V; CL = 15 pF

-

77

-

MHz

CPD

power

dissipation

capacitance

per ﬂip-ﬂop;

VI = GND to VCC

[3]

-30-

-

pF

Table 7.

Dynamic characteristics …continued

GND (ground = 0 V); CL = 50 pF unless otherwise speciﬁed; for test circuit, see Figure 8

Symbol

Parameter

Conditions

25

°C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

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