CS4228A

11

Notes: 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

21. Pin 11 (SCL/CCLK) of the CS4228A does not have sufficient hysteresis to enable the use of standard

two-wire mode configurations with a resistor pull-up. This issue can be worked around by placing a

Schmitt Trigger buffer, for example a 74VHC14, on the SCL line just prior to the CS4228A. See Figure 5.

This will not affect the operation of the bus in either mode, as pin 6 is an input only.

Parameter

Symbol

Min

Max

Units

Ω to ground)

SCL Clock Frequency

-100

kHz

Bus Free Time Between Transmissions

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

4.0

µs

Clock Low Time

4.7

µs

Clock High Time

4.0

µs

Setup Time for Repeated Start Condition

4.7

µs

SDA Hold Time from SCL Falling

(Note 20)

0

µs

SDA Setup Time to SCL Rising

250

ns

Rise Time of Both SDA and SCL Lines

(Note 21)

30

ns

Fall Time of Both SDA and SCL Lines

300

ns

Setup Time for Stop Condition

4.7

µs

t

buf

t

hdst

t

hdst

t

lo w

t r

t f

t

hdd

t

high

t sud

t sust

t susp

Stop

S ta rt

Sta rt

Stop

R e p eated

SD A

SC L

Pi n 1 1

V+

SC L