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TDA6651TT датащи(PDF) 10 Page - NXP Semiconductors |
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TDA6651TT датащи(HTML) 10 Page - NXP Semiconductors |
10 / 54 page TDA6650TT_6651TT_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 10 January 2007 10 of 54 NXP Semiconductors TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer 8.1.1 I2C-bus address selection The device address contains programmable address bits MA1 and MA0, which offer the possibility of having up to four MOPLL ICs in one system. Table 8 gives the relationship between the voltage applied to the AS input and the MA1 and MA0 bits. 8.1.2 XTOUT output buffer and mode setting The crystal frequency can be sent to pin XTOUT and used in the application, for example to drive the clock input of a digital demodulator, saving a quartz crystal in the bill of material. To output fxtal, it is necessary to set T[2:0] to 001. If the output signal on this pin is not used, it is recommended to disable it, by setting T[2:0] to 000. This pin is also used to output 1 ⁄ 2fdiv and fcomp in a test mode. At power-on, the XTOUT output buffer is set to on, supplying the fxtal signal. The relation between the signal on pin XTOUT and the setting of the T[2:0] bits is given in Table 9. [1] Automatic Loop Bandwidth Control (ALBC) is disabled at power-on reset. After power-on reset this feature is enabled by setting T[2:0] = 011. To disable again the ALBC, set T[2:0] = 011 again. This test mode acts like a toggle switch, which means each time it is set the status of the ALBC changes. To toggle the ALBC, two consecutive Control byte 1s (CB1), should be sent: one byte with T[2:0] = 011 indicating that ALBC will be switched on or off and one byte programming the test mode to be selected (see Table 30, example of I2C-bus sequence). [2] This is the default mode at power-on reset. This mode disables the tuning voltage. 8.1.3 Step frequency setting The step frequency is set by three bits, giving five steps to cope with different application requirements. The reference divider ratio is automatically set depending on bits R2, R1 and R0. The phase detector works at either 4 MHz, 2 MHz or 1 MHz. Table 10 shows the step frequencies and corresponding reference divider ratios. When the value of bits R2, R1 and R0 are changed, it is necessary to re-send the data bytes DB1 and DB2. Table 8. Address selection Voltage applied to pin AS MA1 MA0 0 V to 0.1VCC 00 0.2VCC to 0.3VCC or open-circuit 0 1 0.4VCC to 0.6VCC 10 0.9VCC to VCC 11 Table 9. XTOUT buffer status and test modes T2 T1 T0 Pin XTOUT Mode 0 0 0 disabled normal mode with XTOUT buffer off 001fxtal (4 MHz) normal mode with XTOUT buffer on 010 1 ⁄2fdiv charge pump off 011fxtal (4 MHz) switch ALBC on or off[1] 100fcomp test mode 101 1 ⁄2fdiv test mode 110fxtal (4 MHz) charge pump sinking current[2] 1 1 1 disabled charge pump sourcing current |
Аналогичный номер детали - TDA6651TT |
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Аналогичное описание - TDA6651TT |
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