поискавой системы для электроныых деталей |
|
CAT24C21YE-T3 датащи(PDF) 7 Page - ON Semiconductor |
|
CAT24C21YE-T3 датащи(HTML) 7 Page - ON Semiconductor |
7 / 14 page CAT24C21 http://onsemi.com 7 Write Protection When the VCLK pin is connected to GND and the CAT24C21 is in the bi−directional mode, the entire memory is protected and becomes “read only”. Read Operations The READ operation for the CAT24C21 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The CAT24C21’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1 (Figure 12). If N = 127, then the counter will ‘wrap around’ to address 0 and continue to clock out data. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation (Figure 13). The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24C21 acknowledges the word address, the Master device resends the START condition and the slave address, this time with the R/ W bit set to one. The CAT24C21 then responds with its ACK and sends the 8−bit byte requested. The master device does not send an ACK but will generate a STOP condition. Sequential Read The Sequential READ operation (Figure 14) can be initiated by either the Immediate Address READ or the Selective READ operation. After the CAT24C21 sends the first 8−bit byte, the Master responds with an ACK, which tells the Slave that more data is being requested. The CAT24C21 will continue to output an 8−bit byte for each ACK sent by the Master. The entire memory content can thus be read out sequentially. If the end of memory is reached in the process, then addressing will ‘wrap−around’ to the beginning of memory. Data output will stop when the Master fails to acknowledge and sends a STOP condition. Figure 10. Byte Write Timing BYTE ADDRESS SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T ** * * nMAX = 7FH P = 15 for CAT24WC21 * = Don−t care Figure 11. Page Write Timing BUS ACTIVITY: MASTER SDA LINE DATA n+P BYTE ADDRESS (n) A C K A C K DATA n A C K S T O P S A C K DATA n+1 A C K S T A R T P SLAVE ADDRESS * ** * |
Аналогичный номер детали - CAT24C21YE-T3 |
|
Аналогичное описание - CAT24C21YE-T3 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |