MOTOROLA CMOS LOGIC DATA

MC14016B

68

Figure 1. Input Voltage Test Circuit

VC

Vin

Vout

IS

VIL: VC is raised from VSS until VC = VIL.

VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.

Figure 2. Quiescent Power Dissipation

Test Circuit

Figure 3. Typical Power Dissipation per Circuit

(1/4 of device shown)

PULSE

GENERATOR

VDD

10 k

ID

VDD

Vout

VSS

Vin

fc

TO ALL

4 CIRCUITS

PD = VDD x ID

50 M

10 M

1.0 M

100 k

10 k

5.0 k

10,000

1000

100

10

1.0

TA = 25°C

10 Vdc

5.0 Vdc

fc, FREQUENCY (Hz)

CONTROL

INPUT

VDD = 15 Vdc

TYPICAL RON versus INPUT VOLTAGE

Figure 4. VSS = – 5.0 V and – 7.5 V

Figure 5. VSS = 0 V

700

600

500

400

300

200

100

0

– 10 – 8.0

– 4.0

0

4.0

8.0

10

Vin, INPUT VOLTAGE (Vdc)

700

600

500

400

300

200

100

0

0

2.0

6.0

10

14

18

20

Vin, INPUT VOLTAGE (Vdc)

RL = 10 kΩ

TA = 25°C

VC = VDD = 5.0 Vdc

VSS = – 5.0 Vdc

VC = VDD = 7.5 Vdc

VSS = – 7.5 Vdc

VSS = 0 Vdc

RL = 10 kΩ

TA = 25°C

VC = VDD = 10 Vdc

VC = VDD = 15 Vdc