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TPS658621A датащи(PDF) 80 Page - Texas Instruments |
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TPS658621A датащи(HTML) 80 Page - Texas Instruments |
80 / 107 page TPS658621A SLVSA58 – DECEMBER 2009 www.ti.com A simplified block diagram for the ADC analog section is show in Figure 3-22. Figure 3-22. Simplified ADC Block 3.62.1 ADC External Input Pins – Bias Current Settings The external pins ANLG1, ANLG2 and ANLG3 may be biased using internal pull-up current sources, with current source value set by register ADCANLG. The current sources are turned OFF when the ADC reference is disabled. Table 3-58. ADC Input Bias Selection ADCANLG [Addr 0x60] Default to 0 Bit Name ANLG2FLT ANLG3FLT IANLG3[1] IANLG3[0] IANLG2[1] IANLG2[0] IANLG1[1] IANLG1[0] Function SPARE SPARE ANLG3 BIAS CURRENT SOURCE ANLG2 BIAS CURRENT SOURCE ANLG1 BIAS CURRENT SOURCE Table 3-59. ANLG3/2/1 Current Source Settings IANLG[1] IANLG[0] Current ( μA) 0 0 0 0 1 3 1 0 10 1 1 50 The COMP pin has no internal pull-up current source. 3.62.2 ADC Timing Engine Overview The ADC timing engine can be configured to perform either one reading, a single-trigger multiple set of readings, or to operate continuously until high or low limits are violated on any channel. A conversion cycle includes the following steps: 1. Program the timing engine mode (single sample, multiple sample, etc.) and triggers 2. Enable the internal ADC reference and conversion start delay 80 DETAILED DESCRIPTION Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS658621A |
Аналогичный номер детали - TPS658621A |
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Аналогичное описание - TPS658621A |
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