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TPS658621A датащи(PDF) 30 Page - Texas Instruments

номер детали TPS658621A
подробное описание детали  Advanced Power Management Unit
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TPS658621A
SLVSA58 – DECEMBER 2009
www.ti.com
3.7
I
2C COMMUNICATION PROTOCOL
The following conventions will be used when describing the communication protocol:
CONDITION
CODE
START sent from host
S
STOP sent from host
P
TPS658621A I2C slave address sent from host (WRITE)
hA0
TPS658621A register address sent from TPS658621A (READ)
hA1
Non-valid I2C slave address sent from host
hA_N
Valid TPS658621A register address sent from host
HCMD
Non-valid TPS658621A register address sent from host
HCMD_N
I/O data byte (8 bits) sent from host to TPS658621A
hDATA
I/O data byte (8 bits) sent from TPS658621A to host
bqDATA
Acknowledge (ACK) from host
hA
Not acknowledge (NACK) from host
hN
Acknowledge (ACK) from TPS658621A
bqA
Not acknowledge (NACK) from TPS658621A
bqN
Figure 3-1. I2C Conditions
For normal data transfers, the data line (SDAT or PSDAT) is allowed to change only when the clock line
(SCLK or PSCLK) is low, and one clock pulse is used per bit of data. The data line must remain stable
whenever the clock line is high, as data changes when the clock is high are reserved for indicating the
start and stop conditions. Each data transfer is initiated with a start condition and terminated with a stop
condition.
When addressed, the TPS658621A device generates an acknowledge bit after the reception of each byte
by pulling the data line Low. The master device (microprocessor) must generate an extra clock pulse that
is associated with the acknowledge bit. After the acknowledge/not acknowledge bit, the TPS658621A
leaves the data line high, enabling a STOP condition generation.
3.8
I
2C READ AND WRITE OPERATIONS
The TPS658621A supports the standard I2C one byte Write. The basic I2C read protocol has the following
steps:
1. Host sends a start and sends TPS658621A address
30
DETAILED DESCRIPTION
Copyright © 2009, Texas Instruments Incorporated
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