KM44S32030B

CMOS SDRAM

Rev. 0.1 Jun. 1999

The

data rate Dynamic RAM organized as 4 x 8,388,608 words by 4

bits, fabricated with SAMSUNG

′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programma-

ble burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 Page )

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K Cycle)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

8M x 4Bit x 4 Banks Synchronous DRAM

Bank Select

Data Input Register

8M x 4

8M x 4

Column Decoder

Latency & Burst Length

Programming Register

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

CS

RAS

CAS

WE

DQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

8M x 4

8M x 4

Timing Register

* Samsung Electronics reserves the right to change products or specification without notice.

ORDERING INFORMATION

Part No.

Max Freq.

Interface Package

KM44S32030BT-G/FA

133MHz(CL=3)

LVTTL

54

TSOP(II)

KM44S32030BT-G/F8

125MHz(CL=3)

KM44S32030BT-G/FH

100MHz(CL=2)

KM44S32030BT-G/FL

100MHz(CL=3)

KM44S32030BT-G/F10 66MHz(CL=2 &3)