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DM3730 датащи(PDF) 2 Page - Texas Instruments

номер детали DM3730
подробное описание детали  Applications Processor
Download  268 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

DM3730 датащи(HTML) 2 Page - Texas Instruments

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DM3730, DM3725
SPRS685 – AUGUST 2010
www.ti.com
Pseudo-SRAM
Configurable Priority)
Flexible Asynchronous Protocol
– Comprehensive Power, Reset, and Clock
Control for Interface to Custom Logic
Management
(FPGA, CPLD, ASICs, etc.)
SmartReflexTM Technology
Nonmultiplexed Address/Data Mode
Dynamic Voltage and Frequency Scaling
(Limited 2K-Byte Address Space)
(DVFS)
– 1.8-V I/O and 3.0-V (MMC1 only),
– ARM CortexTM-A8 Core
0.9-V to 1.2-V Adaptive Processor Core
ARMv7 Architecture
Voltage
Trust Zone
0.9-V to 1.1-V Adaptive Core Logic Voltage
Thumb®-2
Note: These are default Operating
MMU Enhancements
Performance Point (OPP) voltages and could
In-Order, Dual-Issue, Superscalar
be optimized to lower values using
Microprocessor Core
SmartReflex AVS.
NEON Multimedia Architecture
– Commercial and Extended Temperature
Grades
Over 2x Performance of ARMv6 SIMD
– Serial Communication
Supports Both Integer and Floating Point
SIMD
5 Multichannel Buffered Serial Ports
(McBSPs)
Jazelle® RCT Execution Environment
Architecture
512 Byte Transmit/Receive Buffer
(McBSP1/3/4/5)
Dynamic Branch Prediction with Branch
Target Address Cache, Global History
5K-Byte Transmit/Receive Buffer
Buffer, and 8-Entry Return Stack
(McBSP2)
Embedded Trace Macrocell (ETM)
SIDETONE Core Support (McBSP2 and
Support for Non-Invasive Debug
3 Only) For Filter, Gain, and Mix
Operations
– ARM Cortex-A8 Memory Architecture:
Direct Interface to I2S and PCM Device
32K-Byte Instruction Cache (4-Way
and T Buses
Set-Associative)
128 Channel Transmit/Receive Mode
32K-Byte Data Cache (4-Way
Set-Associative)
Four Master/Slave Multichannel Serial
Port Interface (McSPI) Ports
256K-Byte L2 Cache
High-Speed/Full-Speed/Low-Speed USB
– 32K-Byte ROM
OTG Subsystem (12-/8-Pin ULPI Interface)
– 64K-Byte Shared SRAM
High-Speed/Full-Speed/Low-Speed
– Endianess:
Multiport USB Host Subsystem
ARM Instructions - Little Endian
12-/8-Pin ULPI Interface or 6-/4-/3-Pin
ARM Data – Configurable
Serial Interface
DSP Instructions/Data - Little Endian
One HDQ/1-Wire Interface
• Removable Media Interfaces:
Four UARTs (One with Infrared Data
– Three Multimedia Card (MMC)/ Secure Digital
Association [IrDA] and Consumer Infrared
(SD) With Secure Data I/O (SDIO)
[CIR] Modes)
• Test Interfaces
Three Master/Slave High-Speed
– IEEE-1149.1 (JTAG) Boundary-Scan
Inter-Integrated Circuit (I2C) Controllers
Compatible
– Camera Image Signal Processing (ISP)
– Embedded Trace Macro Interface (ETM)
CCD and CMOS Imager Interface
– Serial Data Transport Interface (SDTI)
Memory Data Input
• 12 32-bit General Purpose Timers
BT.601/BT.656 Digital YCbCr 4:2:2
• 2 32-bit Watchdog Timers
(8-/10-Bit) Interface
• 1 32-bit Secure Watchdog Timer
Glueless Interface to Common Video
• 1 32-bit 32-kHz Sync Timer
Decoders
• Up to 188 General-Purpose I/O (GPIO) Pins
Resize Engine
(Multiplexed With Other Device Functions)
Resize Images From 1/4x to 4x
• 45-nm CMOS Technology
Separate Horizontal/Vertical Control
• Package-On-Package (POP) Implementation for
– System Direct Memory Access (SDMA)
Memory Stacking (Not Available in CUS
Controller (32 Logical Channels With
2
DM3730, DM3725 Applications Processor
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): DM3730 DM3725


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