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ISL54226IRTZ-T датащи(PDF) 6 Page - Intersil Corporation

номер детали ISL54226IRTZ-T
подробное описание детали  High-Speed USB 2.0 (480Mbps) DPST Switch with Overvoltage Protection (OVP) and Dedicated Charger Port Detection
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производитель  INTERSIL [Intersil Corporation]
домашняя страница  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL54226IRTZ-T датащи(HTML) 6 Page - Intersil Corporation

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ISL54226
6
FN7614.0
July 29, 2010
Positive Supply Current, IDD VDD = 3.6V, OE/ALM = 1.4V
25
-
25
32
µA
Full
-
-
38
µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VOE/ALML VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, VOE/ALMH VDD = 2.7V to 3.6V
Full
1.4
--
V
Input Voltage Low, VOE/ALML VDD = 3.7V to 4.2V
Full
-
-
0.7
V
Input Voltage High, VOE/ALMH VDD = 3.7V to 4.2
Full
1.7
--
V
Input Voltage Low, VOE/ALML VDD = 4.3V to 5.25V
Full
-
-
0.8
V
Input Voltage High, VOE/ALMH VDD = 4.3V to 5.25V
Full
2.0
--
V
Input Current, IOE/ALML
VDD = 5.25V, OE/ALM = 0V
Full
-
-8.2
-
nA
Input Current, IOE/ALMH
VDD = 5.25V, OE/ALM = 5.25V, 4MΩ
Pull-down
Full
-
1.4
-
µA
NOTES:
10. VLOGIC = Input voltage to perform proper function.
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
14. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel
with lowest max rON value.
15. Limits established by characterization and are not production tested.
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VOE/ALMH =1.4V,
VOE/ALML = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 11, 12) TYP
MAX
(Notes 11, 12) UNITS
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
50%
tr < 20ns
tf < 20ns
tOFF
90%
VDD
0V
VINPUT
0V
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
VOUT
V(INPUT)
RL
RL rON
+
------------------------
=
SWITCH
INPUT
VIN
VOUT
RL
CL
Dx
COMx
50
Ω
50pF
GND
VDD
C
OE/ALM
VINPUT


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